Design of CMOS 8-Bit Parallel Adder Energy Efficient Structure using SR-CPL Logic Style

Authors(3) :-Aravinth. T. S, Sundar. R, Felix Muthu

We present high speed and low power 8-Bit parallel adder cells designed with modified SR-CPL logic styles that had a reduced power delay product (PDP) as compared to the previous logics DPL and pass transistor logic. We have carried out a comparison against other parallel adders reported as having a low PDP, in terms of speed and power consumption. All the parallel adders were designed with a 0.18┬Ám CMOS technology virtuoso cadence environment. Simulations of the circuit show that the proposed parallel adders have reduced the power from 0.33mW to 0.24mW.

Authors and Affiliations

Aravinth. T. S
Assistant Professor,Department of Electronics & Communication Engineering, Karpagam Academy of Higher Education (Deemed to be University), Coimbatore, Tamil Nadu, India
Sundar. R
Assistant Professor,Department of Electronics & Communication Engineering, Karpagam Academy of Higher Education (Deemed to be University), Coimbatore, Tamil Nadu, India
Felix Muthu
PG Scholar Department of Electrical & Electronics Engineering Karpagam College of Engineering, Coimbatore, Tamil Nadu, India

SR-CPL logic Styles, PDP, DPL, Pass Transistor, Logic, Virtuoso Cadence Environment.

  1. A. M. Shams and M. Bayoumi, "Performance evaluation of 1-bit CMOS adder cells ", IEEE ISCAS, Orlando, Florida, May 1999, pp. I27 -130.
  2. A.P.Chandrakasan, S.Sheng and R.W.Brodersen, "Lowpower CMOS digital design ", IEEE JSSC, Vol. 27, April 1992, pp. 473-483.
  3. N. Weste and K. Eshraghian, Principles of CMOS design, A system perspective, Addison-Wesley, 1988. 4K. M. Chu and D. Pulfrey, "A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic, "IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp.528-532, Aug.1987.
  4. K. Yano, K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, "A 3.8 ns CMOS 16-b multiplier using complementary pass-transistor logic," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 388-395, Apr. 1990.
  5. M. Suzuki, M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, "A 1.5 ns 32-b CMOS ALU in double pass-transistor logic," IEEE J. Solid-State Circuits, vol. 28, no. 11, pp. 1145-1150, Nov.1993.
  6. R. Zimmerman and W. Fichtner, "Low-power logic styles: CMOS Versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, Jul. 1997.
  7. N. Zhuang and H. Wu, "A new design ofthe CMOSfull adder", IEEE JSSC, Vol. 27, No. 5, May 1992, pp. 840-844
  8. A. M. Shams and M. Bayoumi, "A new cellfor low power adders ", Proceedings of the International MWSCAS, 1995.
  9. C. Chang, J. Gu, and M. Zhang, "A reviewof 0.18-full adder performances for tree structured arithmetic circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686-695, Jun. 2005.
  10. M. Aguirre and M. Linares, "An alternative logic approach to implement high-speed low-power full adder cells," in Proc. SBCCI, Florianopolis, Brazil, Sep. 2005, pp.166-171.
  11. Reto Zimmermann and Wolfgang Fichtner, Fellow, IEEE" Low-Power Logic Styles: CMOS Versus Pass- Transistor Logic" in IEEE Journal Of Solid-State Circuits, Vol. 32, No. 7, July 1997.
  12. Aguirre-Hernandez, Mariano, and Monico Linares- Aranda. "CMOS fulladders for energy-efficient arithmetic applications." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 19.4 (2011): 718-721.
  13. Quintana, J. M., et al. "Low-power logic styles for full- adder circuits."Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on. Vol.3. IEEE, 2001
  14. J Rabaey, A Chandrakasan, and B Nikolic, Digital Integrated Circuits: A Design Perspective. Upper Saddle River, NJ: Prentice-Hall, 2003 4. Vijay, V., J. Prathiba, and S. Niranjan Reddy. "A REVIEW OF THE 0.09 ? m STANDARD FULL ADDERS." International Journal of VLSI Design & Communication Systems 3.3 (2012)

Publication Details

Published in : Volume 3 | Issue 5 | May-June 2017
Date of Publication : 2017-04-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 30-34
Manuscript Number : ICASCT2506
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

Aravinth. T. S, Sundar. R, Felix Muthu, " Design of CMOS 8-Bit Parallel Adder Energy Efficient Structure using SR-CPL Logic Style ", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 3, Issue 5, pp.30-34, May-June-2017.
Journal URL : http://ijsrst.com/ICASCT2506

Article Preview