Design and Benchmarking of Gigabit Transceiver Protocol for 45nm based FPGA

Authors

  • Aniket J. Prajapati  Electronics & Communication, GTU PG School, Gandhinagar, Gujarat, India
  • Himanshu Tyagi  Negative Ion Lab, Institute For Plasma Research (IPR), Gandhinagar, Gujarat, India
  • Naresh Kumar Gardas  Cource Coordinator, Centre For Development of Advanced Computing (C-DAC), Pune, Maharashtra, India

Keywords:

Gigabit Transceiver Protocol, Multi-Giga bit transceiver (MGT), Phase-locked Loop (PLL), ChipScope Pro Analyzer.

Abstract

This paper gives the design of link where the parallel digital data are transmitted serially at the rate of 2.5Gbps on the Spartan 6 evaluation board. The implemented design is to test Gigabit Transceiver Protocol in order to transfer 16-bit parallel data serially over the SMA cable in full duplex mode. The 16-bit Parallel data are transmitted and received by the Serialized/De-serialized (SERDES) using Multi-Giga bit transceiver (MGT) at the clock rate of 125MHz.Gigabit Transceiver Protocol converts the parallel data to serial and serial to parallel. The proposed design is simulated in Xilinx 14.7 and implemented on Spartan 6 FPGA. The serial data are transmitted at the rate of 2.5Gbps over the SMA Cable link.

References

  1. Xilinx.com. (2018). [online] Available at: https://www.xilinx.com/support/documentation/user_guides/ug386.pdf [Accessed 11 Apr. 2018].
  2. Xilinx.com. (2018). [online] Available at: https://www.xilinx.com/support/documentation/ip_documentation/s6_gtpwizard_gsg546.pdf [Accessed 12 Apr. 2018].
  3. Xilinx.com. (2018). [online] Available at: https://www.xilinx.com/support/documentation/ip_documentation/s6_gtpwizard/v1_10/ug546_s6_gtpwizard.pdf [Accessed 12 Apr. 2018].
  4. Xilinx.com. (2018). [online] Available at: https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/chipscope_pro_sw_cores_ug029.pdf [Accessed 13 Apr. 2018].
  5. Xilinx.com. (2018). [online] Available at: https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/ug750.pdf [Accessed 15 Apr. 2018].
  6. Xilinx.com. (2018). [online] Available at: https://www.xilinx.com/support/documentation/boards_and_kits/ug526.pdf [Accessed 16 Apr. 2018].
  7. Xilinx.com. (2018). [online] Available at: https://www.xilinx.com/support/documentation/boards_and_kits/ug527.pdf [Accessed 17 Apr. 2018].

International Journal of Scientific Research in Science and Technology

Downloads

Published

2018-04-30

Issue

Volume 4, Issue 7, March-April-2018

Section

Research Articles

License

Copyright (c) IJSRST

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Aniket J. Prajapati, Himanshu Tyagi, Naresh Kumar Gardas, " Design and Benchmarking of Gigabit Transceiver Protocol for 45nm based FPGA, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 4, Issue 7, pp.222-226, March-April-2018.