Design and Benchmarking of Gigabit Transceiver Protocol for 45nm based FPGA

Authors(3) :-Aniket J. Prajapati, Himanshu Tyagi, Naresh Kumar Gardas

This paper gives the design of link where the parallel digital data are transmitted serially at the rate of 2.5Gbps on the Spartan 6 evaluation board. The implemented design is to test Gigabit Transceiver Protocol in order to transfer 16-bit parallel data serially over the SMA cable in full duplex mode. The 16-bit Parallel data are transmitted and received by the Serialized/De-serialized (SERDES) using Multi-Giga bit transceiver (MGT) at the clock rate of 125MHz.Gigabit Transceiver Protocol converts the parallel data to serial and serial to parallel. The proposed design is simulated in Xilinx 14.7 and implemented on Spartan 6 FPGA. The serial data are transmitted at the rate of 2.5Gbps over the SMA Cable link.

Authors and Affiliations

Aniket J. Prajapati
Electronics & Communication, GTU PG School, Gandhinagar, Gujarat, India
Himanshu Tyagi
Negative Ion Lab, Institute For Plasma Research (IPR), Gandhinagar, Gujarat, India
Naresh Kumar Gardas
Cource Coordinator, Centre For Development of Advanced Computing (C-DAC), Pune, Maharashtra, India

Gigabit Transceiver Protocol, Multi-Giga bit transceiver (MGT), Phase-locked Loop (PLL), ChipScope Pro Analyzer.

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Publication Details

Published in : Volume 4 | Issue 7 | March-April 2018
Date of Publication : 2018-04-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 222-226
Manuscript Number : IJSRST11845426
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

Aniket J. Prajapati, Himanshu Tyagi, Naresh Kumar Gardas, " Design and Benchmarking of Gigabit Transceiver Protocol for 45nm based FPGA", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 4, Issue 7, pp.222-226, March-April-2018.
Journal URL : http://ijsrst.com/IJSRST11845426

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