Light-weight Process variation-aware instruction distribution algorithm for Embedded GPUs

Abstract

In the Embedded systems, Graphics Processing Units (GPUs) are used to manage the huge number of computation and to convince the timing limit. Future size, chip aging and die-parameter variations are challenging issues in GPUs. To solve the process variation issues, some processors operate lowest operating frequency in chip-level guard banding, that effects reduce the performance in chip-level. Some other processors improve their performance through core-level guard banding that possibly use various operating frequency for every core. Presents of Process variation, each cluster has a dissimilar level of degradation for the equal amount of instructions. For that reason, a process variation-aware instruction distribution algorithm is essential to balance the stress across the embedded GPU. Suggested light-weight process variation-aware instruction distribution algorithm estimate weight factor of the process variation, level of stress, the current aging status, cluster information (availability and operating frequency) and hierarchy of Real-time Application then gives a various level of instructions to clusters to reduce the aging effect. Simulation results shown that suggested technique improved the GPU aging in 85% and reduce the 40% overhead than compiler-based technique.