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Performance Analysis of CMOS Circuit by Using Sub Clock Power Gating Method
Authors(2) :-C. Indumathi, S. P. Kesavan
Reducing the power consumed by the device is the emerging trend now-a-days. The aim is to reduce the leakage current of the circuit by using the Sub Clocking technology. It is the process of switching the circuit by means of partially ON to reduce the power consumption. There are two modes of operation are implemented. Half Mode Operation (HMO), Full Mode Operation (FMO). These modes of operation are implemented in the two designing methods One is Design-I,In that pMOS and nMOS are connected at header side of the standard CMOS circuit. In Design-II pMOS and nMOS are connected at the footer side of the standard CMOS circuit. pMOS and nMOS transistor at the header and footer side are refer to be as a Sub Clock control unit. Any one of the transistor is ON for a half mode operation and both the transistor are turn ON for full mode of operation. This will do by using the control signal to the sub clock unit which is placed in either header side or footer side of the CMOS gate. By this process the power consumed by the gate is reduced and also reduce the power leakage during the ideal mode of the gate.
C. Indumathi, S. P. Kesavan
Corresponding MOS, Dual Mode Logic (DML), Static Power, Dynamic Power
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Published in : Volume 2 | Issue 2 | March-April 2016
Date of Publication : 2016-04-30
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 282-285
Manuscript Number : IJSRST162299
Publisher : Technoscience Academy
PRINT ISSN : 2395-6011
ONLINE ISSN : 2395-602X
Cite This Article :
C. Indumathi, S. P. Kesavan, "Performance Analysis of CMOS Circuit by Using Sub Clock Power Gating Method", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 2, Issue 2, pp.282-285, March-April-2016.
Journal URL : http://ijsrst.com/IJSRST162299