Performance Analysis of CMOS Circuit by Using Sub Clock Power Gating Method

Authors(2) :-C. Indumathi, S. P. Kesavan

Reducing the power consumed by the device is the emerging trend now-a-days. The aim is to reduce the leakage current of the circuit by using the Sub Clocking technology. It is the process of switching the circuit by means of partially ON to reduce the power consumption. There are two modes of operation are implemented. Half Mode Operation (HMO), Full Mode Operation (FMO). These modes of operation are implemented in the two designing methods One is Design-I,In that pMOS and nMOS are connected at header side of the standard CMOS circuit. In Design-II pMOS and nMOS are connected at the footer side of the standard CMOS circuit. pMOS and nMOS transistor at the header and footer side are refer to be as a Sub Clock control unit. Any one of the transistor is ON for a half mode operation and both the transistor are turn ON for full mode of operation. This will do by using the control signal to the sub clock unit which is placed in either header side or footer side of the CMOS gate. By this process the power consumed by the gate is reduced and also reduce the power leakage during the ideal mode of the gate.

Authors and Affiliations

C. Indumathi
Department of ECE, Nandha College of technology, Erode, Tamil Nadu, India
S. P. Kesavan
Department of ECE, Nandha College of technology, Erode, Tamil Nadu, India

Corresponding MOS, Dual Mode Logic (DML), Static Power, Dynamic Power

  1. Asaf Kaizerman, Sagi Fisher and alexander Fish (2013), 'Subthreshold Dual Mode Logic' IEEE Transactions on Very large scale integration system vol..21 NO.5,pp. 979-983.
  2. Alioto. M (2012), 'Ultralow power VLSI circuit design demystified and explained: A tutorial' IEEE Trans. Circuits Syst. I, vol. 59, No. 1, pp. 3–29.
  3. Bol. D, Ambroise. R, Flandre. D, and Legat. J.D (2008) 'Analysis and minimization of practical energy in 45 nm subthreshold logic circuits' in Proc. IEEE Int. Conf. Comput. Design, pp.294–300.
  4. Calhoun. B. H, Wang. A, and Chandrakasan. A (2005), 'Modeling and sizing for minimum energy operation in subthreshold circuits' IEEE J. Solid-State Circuits, vol. 40, No. 9, pp. 1778–1786.
  5. Chang. M.H, Hsieh. C.Y, Chen. M.W, and Hwang (2015) W, 'Logical effort models with voltage and temperature extensions in super-/near-/sub-threshold regions' in Proc. VLSI Design, Autom. Test (VLSI-DAT), Int.Symp. pp. 1–4.
  6. Kwong. J and Chandrakasan. A.P (2006) 'Variation-driven device sizing for minimum energy sub-threshold circuits'Int. Symp. Low PowerElectron. Design, pp. 8–13.
  7. Levi, Kaizerman. A, and Fish. A (2012), 'Low voltage dual mode logic: Model analysis and parameter extraction'Excepted Elsevier, Micro electron J.,vol. 12, No. 9, pp. 1778–1786.
  8. Liu. X, Zheng. Y, Phyu. M.W, Endru F.W, Navaneethan. V, and Zhao. B (2012), 'An ultra-low power ECG acquisition and monitoring ASIC system for WBAN applications' IEEE J. Emerging Sel. Topics Circuits Syst., vol. 2, No. 1, pp. 60–70.
  9. Markovic.D, Wang. C.C, Alarcon. L.P, and RabaeyJ.M (2010) 'Ultralow power design in near-threshold region' Proc. IEEE, vol. 98, No. 2, pp. 237–252.
  10. Morgenshtein. E.G, Friedman, Ginosar. R, and Kolodny. A (2010), 'Unified logical effort-a method for delay evaluation and minimization in logic paths with interconnect' IEEE Trans. Very Large Scale Integr. (VLSI)Syst., vol. 18, No. 5, pp. 689–696.
  11. Pu. Y, de Gyvez. J.P, Corporaal. H (2009) 'An ultralowenergy/ frame multi-standard JPEG co-processor in 65 nm CMOS with sub/near-threshold power supply,' in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 146–147.
  12. Razak. H (2008)High Performance ASIC Design: Using Synthesizable Domino Logic in an ASIC Flow. Cambridge, U.K.: Cambridge Univ.

Publication Details

Published in : Volume 2 | Issue 2 | March-April 2016
Date of Publication : 2016-04-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 282-285
Manuscript Number : IJSRST162299
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

C. Indumathi, S. P. Kesavan, " Performance Analysis of CMOS Circuit by Using Sub Clock Power Gating Method", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 2, Issue 2, pp.282-285, March-April-2016.
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