VLSI architecture of configurable low complexity hard decision Viterbi decoder

Authors(1) :-Prashant Shirke

A Viterbi algorithm has served as a powerful method for decoding of the convolutional code so as to control errors in data transmission over a noisy channel. It is based on maximum likelihood algorithm for decoding the data. However, the hardware implementation of Viterbi algorithm become crucial as it consumes large resources due to its complexity. This paper discusses the implementation of an efficient VHDL implementation of a Viterbi decoder using the concept of pipelining to reduce the critical path (maximum combinational path delay), thereby improving the operating frequency of the design and improving the throughput using ModelSim and Xilinx ISE tools for simulation and synthesis of modules respectively.

Authors and Affiliations

Prashant Shirke
Electronics Department, G. H. Raisoni College of Engineering, Nagpur, Maharashtra, India

Error correction codes; Maximum likelihood decoding; Convolutional codes; Viterbi algorithm, VHDL

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Publication Details

Published in : Volume 3 | Issue 4 | May-June 2017
Date of Publication : 2017-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 13-19
Manuscript Number : IJSRST1733212
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

Prashant Shirke , " VLSI architecture of configurable low complexity hard decision Viterbi decoder", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 3, Issue 4, pp.13-19, May-June-2017.
Journal URL : http://ijsrst.com/IJSRST1733212

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