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VLSI architecture of configurable low complexity hard decision Viterbi decoder
Authors(1) :-Prashant Shirke
A Viterbi algorithm has served as a powerful method for decoding of the convolutional code so as to control errors in data transmission over a noisy channel. It is based on maximum likelihood algorithm for decoding the data. However, the hardware implementation of Viterbi algorithm become crucial as it consumes large resources due to its complexity. This paper discusses the implementation of an efficient VHDL implementation of a Viterbi decoder using the concept of pipelining to reduce the critical path (maximum combinational path delay), thereby improving the operating frequency of the design and improving the throughput using ModelSim and Xilinx ISE tools for simulation and synthesis of modules respectively.
Error correction codes; Maximum likelihood decoding; Convolutional codes; Viterbi algorithm, VHDL
- A. J. Viterbi, “Convolutional codes and their performance in communication systems,” IEEE Transactions on Communication Technology, vol. COM-19, pp. 751-772, Oct. 1971.
- P. Singh, S. Vishvakarma, “RTL level implementation of high speed- low power viterbi encoder & decoder,” Proc. IEEE ICIST 2013 pp. 345-347, March 2013.
- G. Ungerboeck , “Trellis coded modulation with redundant single set part I : Introduction” IEEE Journal of communication Magazine, vol 25,no 2, pp.5-11, February 1987.
- M. Veshala, T. Padmaja, K. Ghanta, “FPGA based design and implementation of modified viterbi decoder for a wi-fi receiver ,” Proc. IEEE ICT 2013, pp. 525-529, April 2013.
- D. Chakraborty, P. Raha, A. Bhattacharya, R dutta, “Speed optimization of a FPGA based modified Viterbi Decoder,” Proc. IEEE ICCCI 2013, pp. 1-6, January 2013.
- Kelvin Yi- Tse Lai, “An efficient metric normalization architecture for high-speed low-power viterbi decoder” Proc. IEEE TENCON 2007.
- Shu Lin and Costello, “Convolutional Codes”, in Error Control Coding , 2nd ed, India: Dorling Kindersley Pvt. Ltd., 2011, pp. 454-485.
- H-D Lin, “Architectures for Viterbi Decoding and ML Estimators for Controllable Markov Sources,” Master’s thesis, University of California at Berkeley, May. 1988.
- G. Ungerboeck, “Adaptive maximum likelihood receiver for carrier modulated data-transmission systems,” IEEE Trans. Communications, Vol. 22, no. 5, pp. 626-636, May. 1974.
- C. B. Shung, P. H. Siegel, G. Ungerboeck, and H. K. Thaper, “VLSI architectures for metric normalization in the Viterbi algorithm,” IEEE ICC, Vol. 4, pp. 1723-1728, Apr. 1990.
Published in : Volume 3 | Issue 4 | May-June 2017
Date of Publication : 2017-06-30
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 13-19
Manuscript Number : IJSRST1733212
Publisher : Technoscience Academy
PRINT ISSN : 2395-6011
ONLINE ISSN : 2395-602X
Cite This Article :
Prashant Shirke , "VLSI architecture of configurable low complexity hard decision Viterbi decoder", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 3, Issue 4, pp.13-19, May-June-2017
URL : http://ijsrst.com/IJSRST1733212