Vedic Multiplier Using Efficient Compressor to Reduce Delay for Vedic Multiplier : A Review

Authors

  • Ankita V. Rekkawar  M. Tech Scholar, Dept of Electronics and Comm., Ballarpur Institute of Technology, Ballarpur, Maharashtra, India
  • Prof. Atul Khode  Assistant Professor, Dept of Electronics and Comm., Ballarpur Institute of Technology, Ballarpur, Maharashtra, India
  • Prof. S Kuntawar  Assistant Professor, Dept of Electronics and Comm., Ballarpur Institute of Technology, Ballarpur, Maharashtra, India

Keywords:

R High Speed Multiplier, 4:2 Compressors, 7:2 Compressor, Modified Architecture, Vedic Mathematics, Array Multiplier, FPGA.

Abstract

With the coming of new innovation in the space of VLSI, correspondence and flag handling, there is a perpetually going interest for the rapid preparing and low territory design. The speed of a processor enormously relies on upon its time rather than a full snake and equipped for playing out this current multiplier's execution. This thusly builds the interest for fast multipliers, in the meantime remembering low territory and direct power utilization . In the course of recent decades, a few new structures of multipliers have been composed and investigated. Multipliers in view of the Booth's and changed Booth's calculation is very well known in present day VLSI configuration however joined their own arrangement of drawbacks. In these calculations, the increase procedure, includes a few middle of the road operation before touching base at the last answer.

References

  1. L. Sriraman, T.N. Prabakar, “Design and Implementationof TwoVariable Multiplier Using  KCM and  Vedic Mathematics,” 1st Int.Conf.on Recent Advances in Information Technology, Dhanbad,India  2012,IEEE Proc., pp.    782-787.
  2. M. Ramalatha, K. Deena Dayalan, S. Deborah Priya, “High     Speed Energy Efficient ALU Design using Multiplication Techniques,” Advances in  Computational Tools for Engineering Applications, 2009, IEEE Proc., pp 600-603.
  3. Tiwari, Honey Durga, et al., "Multiplier design based on ancient  IndianVedic Mathematics," Int. SoC  Design Conf., 2008, vol. 2. IEEE Proc.,pp. II-65 - II-68.
  4. Sushma R. Huddar Sudhir Rao , Kalpana M and Surabhi Mohan,”Novel High Speed Vedic Mathematics Multiplier using Compressors” IEEE Conf.VLSI,  pp.465-469, 2013.
  5. Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, “Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda,” pp. 5-45, MotilalBanarasida Publishers, Delhi, 2009.
  6. HimanshuThapliyal and M. B. Srinivas, “An efficient method of ellipticcurve encryption using Ancient Indian Vedic Mathematics,” 48th IEEE PInt. Midwest Symp. On Circuits and Systems, 2005, vol. 1, pp. 826-828.
  7. Hsiao, Shen-Fu, Ming-Roun Jiang, and Jia-SienYeh, "Design of  high speed low-power 3-2 counter and 4-2 compressor for fast multipliers”. IEEE Electronics Letters, vol. 34, no.4, pp. 341-343, Feb. 1998.

International Journal of Scientific Research in Science and Technology

Downloads

Published

2017-06-30

Issue

Volume 3, Issue 4, May-June-2017

Section

Research Articles

License

Copyright (c) IJSRST

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Ankita V. Rekkawar, Prof. Atul Khode, Prof. S Kuntawar, " Vedic Multiplier Using Efficient Compressor to Reduce Delay for Vedic Multiplier : A Review, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 3, Issue 4, pp.250-253, May-June-2017.