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Vedic Multiplier Using Efficient Compressor to Reduce Delay for Vedic Multiplier : A Review
Authors(3) :-Ankita V. Rekkawar, Prof. Atul Khode, Prof. S Kuntawar
With the coming of new innovation in the space of VLSI, correspondence and flag handling, there is a perpetually going interest for the rapid preparing and low territory design. The speed of a processor enormously relies on upon its time rather than a full snake and equipped for playing out this current multiplier's execution. This thusly builds the interest for fast multipliers, in the meantime remembering low territory and direct power utilization . In the course of recent decades, a few new structures of multipliers have been composed and investigated. Multipliers in view of the Booth's and changed Booth's calculation is very well known in present day VLSI configuration however joined their own arrangement of drawbacks. In these calculations, the increase procedure, includes a few middle of the road operation before touching base at the last answer.
Ankita V. Rekkawar, Prof. Atul Khode, Prof. S Kuntawar
R High Speed Multiplier, 4:2 Compressors, 7:2 Compressor, Modified Architecture, Vedic Mathematics, Array Multiplier, FPGA.
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Published in : Volume 3 | Issue 4 | May-June 2017
Date of Publication : 2017-06-30
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 250-253
Manuscript Number : IJSRST173458
Publisher : Technoscience Academy
PRINT ISSN : 2395-6011
ONLINE ISSN : 2395-602X
Cite This Article :
Ankita V. Rekkawar, Prof. Atul Khode, Prof. S Kuntawar, "Vedic Multiplier Using Efficient Compressor to Reduce Delay for Vedic Multiplier : A Review", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 3, Issue 4, pp.250-253, May-June-2017.
Journal URL : http://ijsrst.com/IJSRST173458