High Performance and Area Efficient DSP Architecture using Dadda Multiplier
Keywords:
Carry Save, Modified Booth Multiplier, Dadda Multiplier.Abstract
Modern embedded structures required to implement high-end software domain in Digital Signal Processing (DSP). Now-a-days multipliers and DSP functions plays significant role to do fast computations. The efficient DSP functions are implemented by adopting the functions of flexible data path architecture with Modified Booth (MB) multiplier using Carry save arithmetic adder from previous works and now it was extended with Dadda multiplier using CS (Carry Save). In this architecture the structure comprising of flexible computational unit (FCU) in Dadda multiplier with CS to perform fast DSP functions. The flexible DSP functions used to increase the performance by reduce the area, power and delay with carry save arithmetic level abstraction entity were proposed. The FCU architecture design of Dadda multiplier with CS results considerable compressions in power, area and combinational path delay as 12.7%, 4.8%, and 3.9% respectively compared with the MB multiplier with CS.
References
- Kostas Tsoumanis, Sotirios Xydis, Georgios Zervakis, and Kiamal Pekmestzi “Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. Vol. 24, No. 1, January 2016.
- S. Xydis, G. Economakos, D. Soudris, and K. Pekmestzi, “High performance and area efficient flexible DSP datapath synthesis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 3, pp. 429–442, Mar. 2011.
- R. Kastner, A. Kaplan, S. O. Memik, and E. Bozorgzadeh, “Instruction generation for hybrid reconfigurable systems,” ACM Trans. Design Autom. Electron. Syst., vol. 7, no. 4, pp. 605–627, Oct. 2002.
- A. K. Verma, P. Brisk, and P. Ienne, “Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 10, pp. 1761–1774, Oct. 2008.
- T. Kim and J. Um, “A practical approach to the synthesis of arithmetic circuits using carry-save-adders,” IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 19, no. 5, pp. 615–624, May 2000.
- Naveen K Gahlan, Prabhat, Jasbir Kaur “Implementation of Wallace Tree Multiplier Using Compressor” International Journal of Computer & Technology, Vol 3 (3), 1194-1199.
- G. Constantinides, P. Y. K. Cheung, and W. Luk, “Synthesis and Optimization of DSP Algorithms” Norwell, MA, USA: Kluwer, 2004
- Y.H. Seo and D.W. Kim, “A new VLSI architecture of parallel multiplier–accumulator based on Radix-2 modified Booth algorithm,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 201–208, Feb. 2010.
- K. Tsoumanis, S. Xydis, C. Efstathiou, N. Moschopoulos, and K. Pekmestzi, “An optimized modified booth recoder for efficient design of the add-multiply operator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 4, pp. 1133–1143, Apr. 2014.
- N.Savithaa, Dr.C.S.Manikandababu “An Efficient Design of Dadda Multiplier Using Compression Techniques” ,International Journal of Advanced Research in Science, Engineering and Technology,Vol. 4, Issue 3 , March 2016.
Downloads
Published
Issue
Section
License
Copyright (c) IJSRST
This work is licensed under a Creative Commons Attribution 4.0 International License.
