Manuscript Number : IJSRST173686
Energy Efficient high Performance Three INPUT EXCLUSIVE-OR/NOR Gate Design
Authors(2) :-Aditya Mishra, Electronics This paper presents highly efficient three inputs Exclusive-OR/NOR gate (XOR/XNOR) cell. The Exclusive-OR/NOR gate (XOR/XNOR) logic gates are the essential blocks of various embedded arithmetic system such as binary full adder, parity generator/checker, binary comparator, and encryption processor. Many circuits have been proposed on full adder and XOR/XNOR gate design that can be categorised in two categories. First one offers full swing output and second one offers partial swing output. The Systematic Cell Design Methodology is partial swing based logic design method which offers less delay and low power consumption at weak logic ‘0’ and logic ‘1’ generation at output. The proposed design is based on pass transistor logic and transmission gate technology. The proposed design consumes 30%, 38%, 33%, 13% and 48% higher dynamic power than XO4, XO7, XO10, Hybrid and LPHSFA, respectively. While the delay time of proposed design is 40%, 40%, 33%, 75% and 81% lower than XRG1, XRG2, XRG3, Hybrid and LPHSFA, respectively. All simulation results have been obtained by using HSPICE schematic simulator based on TSMC 130nm CMOS technology at 1.2 V supply voltages.
Aditya Mishra Hybrid CMOS logic; Exclusive-OR/NOR gate; transmission gate; pass gate; full swing logic. Publication Details
Published in : Volume 3 | Issue 6 | July-August 2017 Article Preview
Department of Electronics & Communication, Vidhyapeeth Institute of Science & Technology, Bhopal, Madhya Pradesh, India
Electronics
Department of Electronics & Communication, Vidhyapeeth Institute of Science & Technology, Bhopal, Madhya Pradesh, India
Date of Publication : 2017-08-31
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 362-367
Manuscript Number : IJSRST173686
Publisher : Technoscience Academy
Journal URL : https://ijsrst.com/IJSRST173686
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