Review of CMOS based XOR/XNORs using Systematic Cell Design Methodology

Authors

  • Ashok Yadav  Department of Electronics and Communication, RKDF Institute of Science & Technology, Bhopal, India
  • Dr. Manish Jain  Department of Electronics and Communication, RKDF Institute of Science & Technology, Bhopal, India

Keywords:

Hybrid CMOS logic; XOR/XNOR gate; partial swing logic; full swing logic.

Abstract

The XOR and XNOR gates are the essential blocks of various digital arithmetic and logical units such as digital adder, digital parity generator/checker, digital comparator, and digital encryption processor. Many circuit topologies have been proposed till now of full adder and XOR/XNOR gate design that can be categorised in two categories. First one offers full swing output and second one offers partial swing output. The Systematic Cell Design Methodology is partial swing based logic design method which offers less delay and low power consumption at weak logic ‘0’ and logic ‘1’ generation at output. This paper concludes a partial swing and pass transistor based XOR/XNOR gate which gives less propagation delay and low power dissipation at a cost of poor driving capability as compared to existing full adder. In this work results are simulated at 1.2Volt and 130nm technology.

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International Journal of Scientific Research in Science and Technology

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Published

2017-08-31

Issue

Volume 3, Issue 6, July-August-2017

Section

Research Articles

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How to Cite

[1]
Ashok Yadav, Dr. Manish Jain, " Review of CMOS based XOR/XNORs using Systematic Cell Design Methodology, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 3, Issue 6, pp.387-391, July-August-2017.