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Area Efficient Speculative Han-Carlson Adder
Authors(1) :-A. Dhanunjaya Reddy
Parallel prefix adders are used to compute the result with fixed delay and high speed. Better results can be produced by using speculation in these adders. Speculation is nothing but an approximation which can increase microprocessor clock frequency by modifying complete logic function with simplified one that speculates and observe the estimated outputs. This paper introduces a new variable delay speculative han-carlson adder which is combination of Brent-kung and Kogge-stone topologies that gives better performances compared to variable delay kogge-stone adder. Speculative han-carlson introduces error detection network which reduces the error occurences when speculation fails compared to former approaches. Both kogge-stone and han-carlson speculative adders are synthesized in the Xilinx tool which tells that speculative han-carlson adders have less area and more speed compared to speculative kogge-stone and kogge-stone respectively. And non-speculative adders give the best outputs when delay constraint is relaxed.
Addition, parallel prefix adders, error detection network speculative adders, variable delay adders, digital arithmetic.
- I. Koren, Computer Arithmetic Algorithms. Natick, MA, USA: A K Peters, 2002.
- R. Zimmermann, "Binary adder architectures for cell-based VLSI andtheir synthesis," Ph.D. thesis, Swiss Federal Institute of Technology,(ETH) Zurich, Zurich, Switzerland, 1998, Hartung-Gorre Verlag.
- R. P. Brent and H. T. Kung, "A regular layout for parallel adders,"IEEE Trans. Comput., vol. C-31, no. 3, pp. 260-264, Mar. 1982.
- P. M. Kogge and H. S. Stone, "A parallel algorithm for the efficientsolution of a general class of recurrence equations," IEEE Trans.Comput., vol. C-22, no. 8, pp. 786-793, Aug. 1973.
- J. Sklansky, "Conditional-sum addition logic," IRE Trans. Electron.Comput., vol. EC-9, pp. 226-231, Jun. 1960.
- T. Han and D. A. Carlson, "Fast area-efficient VLSI adders," in Proc. IEEE 8th Symp. Comput. Arith. (ARITH), May 18-21, 1987, pp. 49-56.
- R. E. Ladner and M. J. Fischer, "Parallel prefix computation," J. ACM,vol. 27, no. 4, pp. 831-838, Oct. 1980.
- S. Knowles, "A Family of Adders," in Proc. 14th IEEE Symp. Comput.Arith., Vail, CO, USA, Jun. 2001, pp. 277-281.
- S.-L. Lu, "Speeding up processing with approximation circuits," Computer,vol. 37, no. 3, pp. 67-73, Mar. 2004.
- N. Zhu, W.-L. Goh, and K.S. Yeo, "An enhanced low-power high speed Adder For Error-Tolerant application," in Proc. 2009 12th Int.Symp. Integr. Circuits (ISIC '09), Dec. 14-16, 2009, pp. 69-72.
- A. K. Verma, P. Brisk, and P. Ienne, "Variable Latency SpeculativeAddition: A New Paradigm for Arithmetic Circuit Design," in Proc.Design, Autom., Test Eur. (DATE '08), Mar. 2008, pp. 1250-1255.
- K. Du, P. Varman, and K. Mohanram, "High performance reliable variable latency carry select addition," in Proc. Design, Autom., Test Eur. Conf. Exhib. (DATE '12), Mar. 2012, pp. 1257-1262.
- B. Parhami, Computer Arithmetic: Algorithms and Hardware Design.New York: Oxford Univ. Press, 2000
- A. Tyagi, "A reduced-area scheme for carry-select adders,"IEEETrans.Comput., vol. 42, no. 10, pp. 1163-1170, Oct. 1993.
- Darjn Esposito, Davide De Caro, Senior Member, IEEE, Ettore Napoli, Nicola Petra, Member, IEEE, and Antonio Giuseppe Maria Strollo, Senior Member, IEEE May.2015.
Published in : Volume 3 | Issue 7 | September-October 2017
Date of Publication : 2017-10-31
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 119-127
Manuscript Number : IJSRST173740
Publisher : Technoscience Academy
PRINT ISSN : 2395-6011
ONLINE ISSN : 2395-602X
Cite This Article :
A. Dhanunjaya Reddy, "Area Efficient Speculative Han-Carlson Adder", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 3, Issue 7, pp.119-127, September-October-2017
URL : http://ijsrst.com/IJSRST173740