Area Efficient Speculative Han-Carlson Adder

Abstract

Parallel prefix adders are used to compute the result with fixed delay and high speed. Better results can be produced by using speculation in these adders. Speculation is nothing but an approximation which can increase microprocessor clock frequency by modifying complete logic function with simplified one that speculates and observe the estimated outputs. This paper introduces a new variable delay speculative han-carlson adder which is combination of Brent-kung and Kogge-stone topologies that gives better performances compared to variable delay kogge-stone adder. Speculative han-carlson introduces error detection network which reduces the error occurences when speculation fails compared to former approaches. Both kogge-stone and han-carlson speculative adders are synthesized in the Xilinx tool which tells that speculative han-carlson adders have less area and more speed compared to speculative kogge-stone and kogge-stone respectively. And non-speculative adders give the best outputs when delay constraint is relaxed.