Input Vector Observing Simultaneous BIST Architecture Utilizing SRAM Cells

Authors

  • P. Kanimozhi  Electronics and Instrumentation Engineering, Trichy, Tamilnadu, India
  • S. Ramalingam  Electronics and Communication Engineering, Trichy, Tamilnadu, India
  • S. Murugesan  Electrical and Electronics Engineering, K. Ramakrishnan College of Technology, Trichy, Tamilnadu, India
  • N. Ramya  Electrical and Electronics Engineering, K. Ramakrishnan College of Technology, Trichy, Tamilnadu, India

Keywords:

BIST architecture, Static-RAM cells, Concurrent test latency, Circuits under test

Abstract

To perform the testing during the normal operation of the circuit without the set of the circuit in offline mode to perform the test by input vector observing simultaneous BIST engineering utilizing SRAM cells. These testing are evaluated on the basics of the hardware overhead and concurrent test latency (CTL), i.e., the time required for the test to complete, whereas the circuit operates normally. A novel input vector monitoring concurrent BIST architecture test is based on the idea of monitoring a set of vectors reaching the circuit inputs during the normal operation using static-RAM like structure to store the relative locations of the vectors that reach the circuit inputs in the appropriate set (window). The proposed scheme is to perform better than previously proposed schemes with respect to hardware overhead and CTL trade off.

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International Journal of Scientific Research in Science and Technology

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Published

2017-12-31

Issue

Volume 3, Issue 8, November-December-2017

Section

Research Articles

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How to Cite

[1]
P. Kanimozhi, S. Ramalingam, S. Murugesan, N. Ramya, " Input Vector Observing Simultaneous BIST Architecture Utilizing SRAM Cells, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 3, Issue 8, pp.506-514, November-December-2017.