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Input Vector Observing Simultaneous BIST Architecture Utilizing SRAM Cells

Authors(4) :-P. Kanimozhi, S. Ramalingam, S. Murugesan, N. Ramya

To perform the testing during the normal operation of the circuit without the set of the circuit in offline mode to perform the test by input vector observing simultaneous BIST engineering utilizing SRAM cells. These testing are evaluated on the basics of the hardware overhead and concurrent test latency (CTL), i.e., the time required for the test to complete, whereas the circuit operates normally. A novel input vector monitoring concurrent BIST architecture test is based on the idea of monitoring a set of vectors reaching the circuit inputs during the normal operation using static-RAM like structure to store the relative locations of the vectors that reach the circuit inputs in the appropriate set (window). The proposed scheme is to perform better than previously proposed schemes with respect to hardware overhead and CTL trade off.
P. Kanimozhi, S. Ramalingam, S. Murugesan, N. Ramya
BIST architecture, Static-RAM cells, Concurrent test latency, Circuits under test
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Publication Details
  Published in : Volume 3 | Issue 8 | November-December 2017
  Date of Publication : 2017-12-31
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 506-514
Manuscript Number : IJSRST1738123
Publisher : Technoscience Academy
PRINT ISSN : 2395-6011
ONLINE ISSN : 2395-602X
Cite This Article :
P. Kanimozhi, S. Ramalingam, S. Murugesan, N. Ramya, "Input Vector Observing Simultaneous BIST Architecture Utilizing SRAM Cells", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 3, Issue 8, pp.506-514, November-December-2017.
Journal URL : http://ijsrst.com/IJSRST1738123