A Review on Architecture of Low Power VLSI Design

Authors(1) :-P. Sayanna

Low-Power circuit designs are the major requirements in today's electronic scenarios. In the existing systems, power-flow was a secondary-activity and all are considering that as a secondary-terminology as well as give more concentration on compatibility, goodput and financial-aspects. This causes a good-and-accurate results in nature of productivity, but in the competitive analysis of VLSI design falls in trouble in case of considering the low-power-consuming devices such as portable-devices like mobiles, head-sets and so on. For this optimization a new device plan is required to make the circuit complexity so simple as well as providing good-level of compatibility and power-wise simpler designing with simple components'. With-the help of recent technologies', a good optimization techniques are proposed in the size of less-than 89nm', but great' in quality of power dispatching' as well as the maintenance of such devices are simple in creature. The major objective of such kind of device-plans are easy to analyze the flow of working as well as easiness in circuit designing, means low complexity, time-saving methodology and provides good backup needs, which supports many portable devices to operate with enhanced power and good-in-operation for long-time without any interruptions.

Authors and Affiliations

P. Sayanna
Associate Professor, Principal for Diploma Polytechnic Department Of ECE Sudheer Reddy College of Engineering & Technology (W) Keshapur Road, Bardipur (Mdl); Dichpally, Nizamabad, Telangana.India.

VLSI-Design, Power-Reduction, Compatibility, High-Accuracy, Low-Power-Manipulation, Low-Power Strategies, Power-Optimization.

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Publication Details

Published in : Volume 3 | Issue 8 | November-December 2017
Date of Publication : 2017-12-31
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 670-674
Manuscript Number : IJSRST1738160
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

P. Sayanna, " A Review on Architecture of Low Power VLSI Design", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 3, Issue 8, pp.670-674, November-December-2017.
Journal URL : http://ijsrst.com/IJSRST1738160

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