Manuscript Number : IJSRST173897
Power Optimization and Assessment of Optimization Using VLSI Techniques
Authors(2) :-Lali RajKumar, Konda Shiva With the advancement in compact, portable and high-density micro-electronic devices and systems, the power dissipated in very large scale integrated (VLSI) design circuits has become a critical concern. Accuracy and efficiency in power estimation involved in the design phase is important in order to meet power specifications without high cost redesign process. This paper, presents a review of the power optimization theory approach and the estimation techniques of recent proposition. VLSI design has fascinating application area for all combination circuit optimization. In virtual context all classical combination optimization issues, occur in natural way as subtasks. The rapid technological advancement and major theoretical concept advances the mathematics of VLSI design, which has changed significantly over the last two decades. This survey paper also gives a recent account on the key factors in optimization design. And presents a survey of layout techniques in order to design low power digital CMOS circuits. It describes the problems faced by the designers at the physical design abstraction and reviews some of the techniques which are proposed to overcome these difficulties.
Lali RajKumar Optimization, VLSI, Physical Design, Layout, Placement, Routing, MED, BDD, CMOS Publication Details
Published in : Volume 3 | Issue 8 | November-December 2017 Article Preview
M.Tech, Department of ECE Aurora Engineering College, Telangana, India
Konda Shiva
M.Tech, Department of ECE Gokaraju Rangaraju Institute of Engineering and Technology, Telangana, India
Date of Publication : 2017-12-31
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 388-393
Manuscript Number : IJSRST173897
Publisher : Technoscience Academy
Journal URL : https://ijsrst.com/IJSRST173897
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