Design of CMOS Phase Locked Loop

Authors(1) :-Kaviyadharshini Sivaraman

This paper focuses on the design and simulation of a phase locked loop (PLL) which is used in communication circuits to select the desired frequency channel. The proposed PLL is designed using 180 nm CMOS/VLSI technology with supply voltage of 1.8v and the results are provided. PLL is an electronic circuit which is used to lock the output frequency of VCO with the desired input frequency by contantly comparing the phase of the input frequency with that of the output frequency of the VCO. Here designed PLL, which locks the communication circuit for 2GHz. A PLL often consists of a phase frequency detector, low pass filter, and a voltageĀ¬ controlled oscillator (VCO).

Authors and Affiliations

Kaviyadharshini Sivaraman
PG Scholar, Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, Tamil Nadu, India

Phase Locked Loop, Low Pass Filter, Voltage Controlled Oscillator, Frequency Divider

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Publication Details

Published in : Volume 4 | Issue 2 | January-February 2018
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1130-1136
Manuscript Number : IJSRST1841231
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

Kaviyadharshini Sivaraman, " Design of CMOS Phase Locked Loop", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 4, Issue 2, pp.1130-1136, January-February-2018.
Journal URL : https://ijsrst.com/IJSRST1841231
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