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FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors

Authors(2) :-IM. Lavanya, A. M. Guna Sekhar

Floating point multiplier is one of the vital concerns in every digital system. In this paper, the concepts of High speed compressors are used for the implementation of a High speed single precision binary Floating point multiplier by using IEEE 754 standard. Since compressors are special kind of adder which is capable to add more number of bits at a time, the use of these compressors makes the multiplier faster as compared to the conventional multiplier. For Mantissa calculation, a 24x24 bit multiplier has been developed by using these compressors. Owing to these high speed compressors, the proposed multiplier is implemented using Verilog HDL and it is simulated and synthesized for Xilinx 14.3.
IM. Lavanya, A. M. Guna Sekhar
Floating Point, Multiplication, Single Precision, Verilog HDL.
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Publication Details
  Published in : Volume 4 | Issue 2 | January-February 2018
  Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 219-225
Manuscript Number : IJSRST184146
Publisher : Technoscience Academy
PRINT ISSN : 2395-6011
ONLINE ISSN : 2395-602X
Cite This Article :
IM. Lavanya, A. M. Guna Sekhar, "FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 4, Issue 2, pp.219-225, January-February-2018
URL : http://ijsrst.com/IJSRST184146