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An Efficient Reversible PLA Implemented In BIST for More Fault Coverage
Authors(3) :-K. Jhansi, Dr. G. N. Kodanda Ramaiah, R. Naresh Naik
Reversible logics are one of the most vital logics in present and it has different areas for its application ,those are low power CMOS, quantum computing, nano technology,digital signal processing etc., Logic synthesis for reversible logic differs considerably from standard logic synthesis. Reversible logic has been motivated by consideration of zero-energy computation thus it reduces the power utilization. A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits,Re- conFigure urability and structural regularity of Programmable Logic Devices caused wide use of it by the logic designers. Here in this paper we propose a design algorithm for a PLA with a newly designed low cost 3×3 reversible NMG circuit for implementing multi-output ESOP (Exclusive-OR Sum of Product) functions. In addition to this work is to make the design efficient reversible PLA implemented in built in self test (BIST) to enhancing the testing properties like power, fault coverage. The total work has been implemented in Xilinx 14.3 tool using verilog code.
K. Jhansi, Dr. G. N. Kodanda Ramaiah, R. Naresh Naik
Reversible Logics, PLA, ESOP,BIST
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Published in : Volume 4 | Issue 2 | January-February 2018
Date of Publication : 2018-02-28
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 226-233
Manuscript Number : IJSRST184172
Publisher : Technoscience Academy
PRINT ISSN : 2395-6011
ONLINE ISSN : 2395-602X
Cite This Article :
K. Jhansi, Dr. G. N. Kodanda Ramaiah, R. Naresh Naik, "An Efficient Reversible PLA Implemented In BIST for More Fault Coverage", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 4, Issue 2, pp.226-233, January-February-2018
URL : http://ijsrst.com/IJSRST184172