Design and Implementation of Parallel Micro-programmed FIR Filter Using Efficient Multipliers on FPGA

Authors(2) :-Cherasala Renuka, A. M. Guna Sekhar

Impulse Response Filter plays an important part in digital signal processing applications such as video, audio and image processing. The performance of FIR filter is improved by using efficient multipliers and adders. In this paper 8 tap parallel microprogrammed FIR filter architecture is implemented using Wallace tree and Vedic multiplier. The designs are realized using Xilinx Virtex-5 FPGA. FPGA results are presented and analyzed. Implementation theresults are presented and analyzed. Based on the implementation results, parallel FIR filter using Wallace tree multiplier/carry skip adder combination proves to be more efficient as compared to other multiplier/adder combinations both Wallace tree and Vedic multiplier compared to the existing work. Hence proposed method is more efficient.

Authors and Affiliations

Cherasala Renuka
M. Tech Student, Sree Rama Engineering College, Tirupathi, India
A. M. Guna Sekhar
Associate Professor, Sree Rama Engineering College, Tirupathi, India

FPGA, FIR filter, parallel micro programed, Multiplier.

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Publication Details

Published in : Volume 4 | Issue 2 | January-February 2018
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 234-238
Manuscript Number : IJSRST184173
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

Cherasala Renuka, A. M. Guna Sekhar, " Design and Implementation of Parallel Micro-programmed FIR Filter Using Efficient Multipliers on FPGA", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 4, Issue 2, pp.234-238, January-February-2018.
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