Design and Implementation of Parallel Micro-programmed FIR Filter Using Efficient Multipliers on FPGA
Keywords:
FPGA, FIR filter, parallel micro programed, Multiplier.Abstract
Impulse Response Filter plays an important part in digital signal processing applications such as video, audio and image processing. The performance of FIR filter is improved by using efficient multipliers and adders. In this paper 8 tap parallel microprogrammed FIR filter architecture is implemented using Wallace tree and Vedic multiplier. The designs are realized using Xilinx Virtex-5 FPGA. FPGA results are presented and analyzed. Implementation theresults are presented and analyzed. Based on the implementation results, parallel FIR filter using Wallace tree multiplier/carry skip adder combination proves to be more efficient as compared to other multiplier/adder combinations both Wallace tree and Vedic multiplier compared to the existing work. Hence proposed method is more efficient.
References
- Abdullah A. AlJuffri, Aiman S. Badawi and Mohammed S. BenSaleh, FPGA Implementation of Scalable Microprogrammed "FIR Filter Architectures using Wallace Tree and Vedic Multipliers," IEEE pp. 159-132 2015
- M. S. BenSaleh, S. M. Qasim, A. A. AlJuffri and A. M. Obeid, "Scalable design of microprogrammed digital FIR filter for sensor processing subsystem," IEICE Electronic Express, Vol. 11, No. 14, pp. 1-7, Aug. 2014.
- Vanga Mahesh and R. Nirmala Devi, "Design and Characterization of Efficient Parallel Prefix Adders using FPGAs," International Journal of Engineering Research & Technology (IJERT), Vol. 3 Issue 9, September 2014
- Wai-leong Pang, Kah-yoong Chan, Sew-kin Wong, Choon-siang Tan, "VHDL Modelling of Booth Radix-4 Floating Point Multiplier for VLSI Designer’s Library," Vol 12, Issue 12, December 2013
- PushpalathaChoppa and B.N. Srinivasa Rao "Implementation of Ripple Carry and Carry Skip Adders with Speed and Area Efficient," International Journal of Advanced Research in Computer and Communication Engineering, Vol. 3, October 2014
- S. M. Qasim, M. S. BenSaleh and A. M. Obeid, "Efficient FPGA implementation of microprogram control unit based FIR filter using Xilinx and Synopsys tools," Proc. of Synopsys Users Group Conference (SNUG), Silicon Valley, USA, pp. 1-14, March 2012.
- M. A. Ashour and H. I. Saleh, "An FPGA implementation guide for some different types of serial-parallel multiplier structures," Microelectroncis J., Vol. 31, PP. 161-168, 2000.
- S. M. Qasim, A. A. Telba and A. Y. AlMazroo, "FPGA design and implementation of matrix multiplier architectures for image and signal processing applications," Int. J. Comp. Sci. Network Security, Vol. 10, No. 2, pp. 168-176, Feb. 2010.
- A. M. Obeid, S. M. Qasim, M. S. BenSaleh, Z. Marrakchi, H. Mehrez, H. Ghariani and M. Abid, "Flexible reconfigurable architecture for DSPapplications," Proc. of 27th IEEE Intl. System-on-Chip Conf. (SOCC),pp. 204-209, Sept. 2014.
- S. M. Qasim, M. S. BenSaleh, M. Bahaidarah, H. AlObaisi, T. AlSharif,M. Alzahrani and H. AlOnazi, "Design and FPGA implementation ofsequential digital FIR filter using microprogrammed controller," Proc.of 4th Intl. Congress on Ultra Modern Telecommunications and ControlSystems and Workshops (ICUMT), pp. 1002-1005, Oct. 2012.
- M. S. BenSaleh, S. M. Qasim, M. Bahaidarah, H. AlObaisi, T. AlSharif, M. Alzahrani and H. AlOnazi, "Field programmable gate arrayrealization of microprogrammed controller based parallel digital FIRfilter architecture," Proc. of World Congress on Engineering andComputer Science (WCECS), pp 828–831, Oct. 2012.
- S. M. Qasim and M. S. BenSaleh, "Hardware implementation ofmicroprogrammed controller based digital FIR filter," IAENG Trans.Engg. Tech., Vol. 247, pp 29-40, 2014.
Downloads
Published
Issue
Section
License
Copyright (c) IJSRST
This work is licensed under a Creative Commons Attribution 4.0 International License.
