VLSI Implementation of High Performance Montgomery Modular Multiplication

Abstract

The multiplier gets and yields the information with paired portrayal and uses just a single level Carry Save Adder (CSA) to maintain a strategic distance from the convey proliferation at every expansion operation. This CSA is additionally used to perform operand pre calculation and arrangement transformation from the convey spare organization to the paired portrayal, prompting a low equipment cost and short basic way delay to the detriment of additional clock cycles for finishing one particular duplication. To conquer the shortcoming, a Configurable CSA (CCSA), which could be one full-viper or two serial half-adders, is proposed to decrease the additional clock cycles for operand pre calculation and organization change significantly. The system that can distinguish and avoid the pointless convey spare expansion operations in the one-level CCSA engineering while at the same time keeping up the short basic way delay is created. The additional clock cycles for operand pre calculation and organization change can be covered up and high throughput can be gotten