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VLSI Implementation of High Performance Montgomery Modular Multiplication

Authors(2) :-M. Sravan Kumar, B. Jyothi Priya

The multiplier gets and yields the information with paired portrayal and uses just a single level Carry Save Adder (CSA) to maintain a strategic distance from the convey proliferation at every expansion operation. This CSA is additionally used to perform operand pre calculation and arrangement transformation from the convey spare organization to the paired portrayal, prompting a low equipment cost and short basic way delay to the detriment of additional clock cycles for finishing one particular duplication. To conquer the shortcoming, a Configurable CSA (CCSA), which could be one full-viper or two serial half-adders, is proposed to decrease the additional clock cycles for operand pre calculation and organization change significantly. The system that can distinguish and avoid the pointless convey spare expansion operations in the one-level CCSA engineering while at the same time keeping up the short basic way delay is created. The additional clock cycles for operand pre calculation and organization change can be covered up and high throughput can be gotten
M. Sravan Kumar, B. Jyothi Priya
CCSA, Clock Cycles, Montgomery Modular Multiplication, VLSI, SCS, FCS
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Publication Details
  Published in : Volume 4 | Issue 2 | January-February 2018
  Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 351-354
Manuscript Number : IJSRST184185
Publisher : Technoscience Academy
PRINT ISSN : 2395-6011
ONLINE ISSN : 2395-602X
Cite This Article :
M. Sravan Kumar, B. Jyothi Priya, "VLSI Implementation of High Performance Montgomery Modular Multiplication", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 4, Issue 2, pp.351-354, January-February-2018
URL : http://ijsrst.com/IJSRST184185