A Normal I/O Order Radix-2 FFT Architecture for High Speed Applications

Authors

  • K. Ravi Kumar   PG Scholar, JNTUA College of Engineering, Anantapuramu, Andhra Pradesh, India

Keywords:

Fast Fourier Transform (FFT), Decimation in Frequency (DIF) FFT, Decimation in Time (DIT) FFT, Bit reversal, Reorder shift registers (RSR), Multipath Delay Commutator (MDC) FFT, Normal Order.

Abstract

Nowadays, many applications require simultaneous computation of multiple independent Fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this paper presents a pipelined Fast Fourier Transform (FFT) processor for the computation of two independent data streams. This architecture is based on the Multipath Delay Commutator (MDC) FFT architecture. It has an N/2-point Decimation In Time (DIT) FFT and an N/2-point Decimation In Frequency (DIF) FFT to process the odd and even samples of two data streams separately. The main feature of this architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by scheduling the data. Therefore the proposed architecture take less time and has a high throughput.

References

  1. S. He and M. Torkelson, "A new approach to pipeline FFT processor,"in Proc. 10th Int. Parallel Process. Symp., 1996, pp. 766-770.
  2. Y. Chen, Y.-W. Lin, Y.-C. Tsao, and C.-Y. Lee, " 2.4-Gsample/s DVFS FFT processor for MIMO OFDM communication systems," IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1260-1273,May 2008.
  3. Chu Yu, Member, IEEE, Mao-Hsu Yen, Pao-Ann Hsiung, Senior Member, IEEE,and Sao-Jie Chen, Senior Member, IEEE," A Low-Power 64-point Pipeline FFT/IFFT Processor for OFDM Applications" IEEE Transactions on Consumer Electronics, Vol. 57, No. 1, February 2011.
  4. K.-J. Yang, S.-H. Tsai, and G. C. H. Chuang, "MDC FFT/IFFT processor with variable length for MIMO-OFDM systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 4, pp. 720-731,Apr. 2013.
  5. M. Garrido, J. Grajal, and O. Gustafsson, "Optimum circuits for bit reversal," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 10, pp. 657-661, Oct. 2011.
  6. Antony Xavier Glittas, Mathini Sellathurai, and Gopalakrishnan Lakshminarayanan "A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams "IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 24, No. 6, June 2016.
  7. S.-G. Chen, S.-J. Huang, M. Garrido, and S.-J. Jou, "Continuous-flow parallel bit-reversal circuit for MDF and MDC FFT architectures," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 10, pp. 2869-2877, Oct. 2014.
  8. M. Garrido, J. Grajal, M. A. Sanchez, and O. Gustafsson, "Pipelined radix-2 feedforward FFT architectures," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 1, pp. 23-32, Jan. 2013.

International Journal of Scientific Research in Science and Technology

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Published

2018-02-28

Issue

Volume 4, Issue 2, January-February-2018

Section

Research Articles

License

Copyright (c) IJSRST

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
K. Ravi Kumar , " A Normal I/O Order Radix-2 FFT Architecture for High Speed Applications, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 4, Issue 2, pp.440-445, January-February-2018.