Implementation of High Speed Double Tail Comparator

Authors(3) :-U. S. Harshanga Kalingage, K.Lokesh Krishna, K.Anuradha

In recent years, with the advance of wireless communication systems, microelectronics and sensor technologies, wireless sensor networks (WSNs) are becoming a hot-spot for scientific research and industrial applications. High speed and low power comparators are very much essential in the design of a very good analog to digital converter. In this paper a novel high speed, low offset voltage and low power double tail comparator is designed and simulated. The proposed design does not use any preamplifier stages before the latch stage, which accounts for the direct reduction of power dissipation and silicon area. For power optimization, the MOSFETs of the input differential pair comparator are designed to operate in sub-threshold region rather than in saturation region. The designed double tail comparator consumes 366µW when operated from a 1.8V power supply. The operating speed of the design is 100MHz and exhibits a propagation delay of 600µs. The simulated propagation delay is found to be 600µs and the entire design of the proposed double tail comparator circuit is carried out in 180nm CMOS technology and verified using the cadence-spectre simulator.

Authors and Affiliations

U. S. Harshanga Kalingage
1ECE Department, SVCET, Chittoor, Andhra Pradesh, India
K.Lokesh Krishna
Department of ECE, S.V.College of Engineering, Tirupati, Andhra Pradesh, India
K.Anuradha
Department of CSE, L.B.C.E.W., Visakhapatnam, Andhra Pradesh, India

high speed, positive feedback, analog to digital converter (ADC), digital to analog converter (DAC), threshold, and offset voltage.

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Publication Details

Published in : Volume 4 | Issue 5 | March-April 2018
Date of Publication : 2018-04-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1064-1068
Manuscript Number : IJSRST1845250
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

U. S. Harshanga Kalingage, K.Lokesh Krishna, K.Anuradha, " Implementation of High Speed Double Tail Comparator", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 4, Issue 5, pp.1064-1068, March-April-2018.
Journal URL : https://ijsrst.com/IJSRST1845250
Citation Detection and Elimination     |      | |
  • Junjie Lu, Jeremy Holleman, "A low-power high-precision comparator with time-domain bulk-tuned offset cancellation", Circuits and Systems I: Regular Papers IEEE Transactions on, vol. 60, no. 5, pp. 1158-1167, 2013.
  • J. C. Jensen, and L. E. Larson, "A 16-GHz ultra-high-speed Si-SiGe HBT comparator," IEEE Journal of Solid-State Circuits, vol. 38, no. 9, pp. 1584-1589, September 2003.
  • K. Deepika, K. Lokesh Krishna, Dr. K. Anuradha, "A Low Power High Speed Double-Tail Comparator in 90nm CMOS Technology", International Journal of Computer Science Trends & Technology (IJCST), Volume 3 Issue 2, ISSN: 2347-8578, pp: 203- 207, Mar-Apr 2015.
  • B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
  • C. R. Grace, P. J. Hurst, S. H. Lewis, "A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration", Solid-State Circuits IEEE J., vol. 40, no. 5, pp. 1038-1046, 2005.
  • S. Babayan-Mashhadi, R. Lotfi, "Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator", Very Large Scale Integr. Syst. IEEE Trans., vol. 22, no. 2, pp. 343-352, 2014.
  • K. L. Krishna, T. Ramashri and D. Reena, "A 1V second order delta sigma ADC in 130nm CMOS," International Conference on Information Communication and Embedded Systems (ICICES2014), Chennai, 2014, pp. 1-5.
  • N. B. Romli, M. Mamun, M. A. S. Bhuiyan, H. Husain, "Design of a low power dissipation and low input voltage range level shifter in CEDEC 0.18-µm CMOS process", World Applied Sciences Journal, vol. 19, pp. 1140-1148, 2012.
  • " target="_blank"> BibTeX
    |
  • Junjie Lu, Jeremy Holleman, "A low-power high-precision comparator with time-domain bulk-tuned offset cancellation", Circuits and Systems I: Regular Papers IEEE Transactions on, vol. 60, no. 5, pp. 1158-1167, 2013.
  • J. C. Jensen, and L. E. Larson, "A 16-GHz ultra-high-speed Si-SiGe HBT comparator," IEEE Journal of Solid-State Circuits, vol. 38, no. 9, pp. 1584-1589, September 2003.
  • K. Deepika, K. Lokesh Krishna, Dr. K. Anuradha, "A Low Power High Speed Double-Tail Comparator in 90nm CMOS Technology", International Journal of Computer Science Trends & Technology (IJCST), Volume 3 Issue 2, ISSN: 2347-8578, pp: 203- 207, Mar-Apr 2015.
  • B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
  • C. R. Grace, P. J. Hurst, S. H. Lewis, "A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration", Solid-State Circuits IEEE J., vol. 40, no. 5, pp. 1038-1046, 2005.
  • S. Babayan-Mashhadi, R. Lotfi, "Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator", Very Large Scale Integr. Syst. IEEE Trans., vol. 22, no. 2, pp. 343-352, 2014.
  • K. L. Krishna, T. Ramashri and D. Reena, "A 1V second order delta sigma ADC in 130nm CMOS," International Conference on Information Communication and Embedded Systems (ICICES2014), Chennai, 2014, pp. 1-5.
  • N. B. Romli, M. Mamun, M. A. S. Bhuiyan, H. Husain, "Design of a low power dissipation and low input voltage range level shifter in CEDEC 0.18-µm CMOS process", World Applied Sciences Journal, vol. 19, pp. 1140-1148, 2012.
  • " target="_blank">RIS
    |
  • Junjie Lu, Jeremy Holleman, "A low-power high-precision comparator with time-domain bulk-tuned offset cancellation", Circuits and Systems I: Regular Papers IEEE Transactions on, vol. 60, no. 5, pp. 1158-1167, 2013.
  • J. C. Jensen, and L. E. Larson, "A 16-GHz ultra-high-speed Si-SiGe HBT comparator," IEEE Journal of Solid-State Circuits, vol. 38, no. 9, pp. 1584-1589, September 2003.
  • K. Deepika, K. Lokesh Krishna, Dr. K. Anuradha, "A Low Power High Speed Double-Tail Comparator in 90nm CMOS Technology", International Journal of Computer Science Trends & Technology (IJCST), Volume 3 Issue 2, ISSN: 2347-8578, pp: 203- 207, Mar-Apr 2015.
  • B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
  • C. R. Grace, P. J. Hurst, S. H. Lewis, "A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration", Solid-State Circuits IEEE J., vol. 40, no. 5, pp. 1038-1046, 2005.
  • S. Babayan-Mashhadi, R. Lotfi, "Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator", Very Large Scale Integr. Syst. IEEE Trans., vol. 22, no. 2, pp. 343-352, 2014.
  • K. L. Krishna, T. Ramashri and D. Reena, "A 1V second order delta sigma ADC in 130nm CMOS," International Conference on Information Communication and Embedded Systems (ICICES2014), Chennai, 2014, pp. 1-5.
  • N. B. Romli, M. Mamun, M. A. S. Bhuiyan, H. Husain, "Design of a low power dissipation and low input voltage range level shifter in CEDEC 0.18-µm CMOS process", World Applied Sciences Journal, vol. 19, pp. 1140-1148, 2012.
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