Manuscript Number : IJSRST184548
Comparative Analysis of Adders Parallel-Prefix Adder for Their Area, Delay and Power Consumption
Authors(2) :-Dr. V. Sidharthan, M. Prasannakumar
Parallel Prefix adders have been one of the most notable among more than a few designs proposed in the past. Parallel Prefix adders (PPA) are family of adders derived from the generally known carry look ahead adders. The need for a PPA is that it is mostly fast when compared with Ripple Carry Adders (RCA). The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, and fan-out and interconnect count of logic circuits. In this paper, a comparison of four 8-bit parallel-Prefix adders (Ladner-Fischer Adder (LFA), Kogge-Stone Adder (KSA), Bent-Kang Adder (BKA) and Han-Carlson Adder (HCA)) in their area, delay, power is proposed. In this proposed system Ladner-Fischer adder, Kogge-Stone adder, Bent-Kang adder and Han-Carlson adder, the Parallel Prefix adder are used for comparison. The results reveal that proposed Han-Carlson adder Parallel-Prefix Adder is more competent than other three types of Parallel-Prefix adder in terms of area, delay & power. Simulation results are compared and verified using Xilinx 8.1i software.
Dr. V. Sidharthan
Parallel-Prefix Adder, Area, Power, Delay
Publication Details
Published in :
Volume 4 | Issue 5 | March-April 2018 Article Preview
Assistant Professor, Department of Electronics, Sri Ramakrishna College of Arts and Science (Autonomous), Nava India, Coimbatore, Tamil Nadu, India
M. Prasannakumar
Assistant Professor, Department of Electronics, Sri Ramakrishna College of Arts and Science (Autonomous), Nava India, Coimbatore, Tamil Nadu, India
Date of Publication :
2018-04-30
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) :
353-357
Manuscript Number :
IJSRST184548
Publisher : Technoscience Academy
Journal URL :
http://ijsrst.com/IJSRST184548