A High-Performance FIR filter Architecture for Reconfigurable Applications

Authors(3) :-R. Yerriswamy, Dr. D. Vishnu Vardhan, Sankar Lal Sharma

Transpose form ?nite-impulse response (FIR) ?lters are characteristically pipelined and support multiple constant multiplications (MCM) procedure that results in signi?cant saving of calculation. However, transpose form con?guration does not specifically support the block performing not like direct-form con?guration. In this paper, we investigate the possibility of realization of block FIR ?lter in transpose shape con?guration for area-delay ef?cient realization of huge order FIR ?lters for both ?xed applications. Based on a detailed computational investigation of transpose form con?guration of FIR ?lter, we have derived a ?ow diagram for transpose shape block FIR ?lter with reduced register complexity. A detailed block formulation is detailed for transpose form FIR ?lter. We have inferred a general multiplier-based architecture for the proposed transpose form block ?lter for recon?gurable applications. A reduced-complex design using multiple constant multiplications scheme is also showed for block implementation of ?xed FIR ?lters. The proposed architecture obtains less area, less delay and less power consumption compared with the existing architecture of direct form structure for medium or long filter lengths. For this project analysis for determining area, power and delay it uses Xilinx.

Authors and Affiliations

R. Yerriswamy
Department of ECE, JNTUA, Andhra Pradesh, India.
Dr. D. Vishnu Vardhan
Department of ECE, JNTUA, Andhra Pradesh, India.
Sankar Lal Sharma
Head, Department of ECE, University College of Engineering and Technology, BIKANER, Rajasthan, India

Finite-Impulse Response (FIR), Block Processing, Reconfigurable Architecture, Multiple Constant Multiplications (MCM).

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Publication Details

Published in : Volume 6 | Issue 1 | January-February 2019
Date of Publication : 2019-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 420-424
Manuscript Number : IJSRST196158
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

R. Yerriswamy, Dr. D. Vishnu Vardhan, Sankar Lal Sharma, " A High-Performance FIR filter Architecture for Reconfigurable Applications", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 6, Issue 1, pp.420-424, January-February-2019. Available at doi : https://doi.org/10.32628/IJSRST196158    
Journal URL : https://ijsrst.com/IJSRST196158
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  • E. Mirchandani, R. L. Zinser, Jr., and J. B. Evans, "A new adaptive noise cancellation scheme in the presence of crosstalk speech signals]," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 10, pp. 681-694, Oct. 1995.
  • D. Xu and J. Chiu, "Design of a high-order FIR digital ?ltering and variable gain ranging seismic data acquisition system," in Proc. IEEE Southeastcon, Apr. 1993, p. 1-6.
  • J. Mitola, Software Radio Architecture: Object-Oriented Approaches to Wireless Systems Engineering. New York, NY, USA: Wiley, 2000.
  • A. P. Vinod and E. M. Lai, "Low power and high-speed implementation of FIR ?lters for software de?ned radio receivers," IEEE Trans. Wireless Commun., vol. 7, no. 5, pp. 1669-1675, Jul. 2006.
  • J. Park, W. Jeong, H. Mahmoodi-Meimand, Y. Wang, H. Choo, and K. Roy, "Computation sharing programmable FIR ?lter for low-power and high-performance applications," IEEE J. Solid State Circuits, vol. 39, no. 2, pp. 348-357, Feb. 2004.
  • K.-H. Chen and T.-D. Chiueh, "A low-power digit-based recon?gurable FIR ?lter," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 617-621, Aug. 2006.
  • R. Mahesh and A. P. Vinod, "New recon?gurable architectures for implementing FIR ?lters with low complexity," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 2, pp. 275-288, Feb. 2010.
  • S. Y. Park and P. K. Meher, "Ef?cient FPGA and ASIC realizations of a DA-based recon?gurable FIR digital ?lter," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 7, pp. 511-515, Jul. 2014.
  • P. K. Meher, "Hardware-ef?cient systolization of DA-based calculation of ?nite digital convolution," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 707-711, Aug. 2006.
  • " target="_blank"> BibTeX
    |
  • E. Mirchandani, R. L. Zinser, Jr., and J. B. Evans, "A new adaptive noise cancellation scheme in the presence of crosstalk speech signals]," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 10, pp. 681-694, Oct. 1995.
  • D. Xu and J. Chiu, "Design of a high-order FIR digital ?ltering and variable gain ranging seismic data acquisition system," in Proc. IEEE Southeastcon, Apr. 1993, p. 1-6.
  • J. Mitola, Software Radio Architecture: Object-Oriented Approaches to Wireless Systems Engineering. New York, NY, USA: Wiley, 2000.
  • A. P. Vinod and E. M. Lai, "Low power and high-speed implementation of FIR ?lters for software de?ned radio receivers," IEEE Trans. Wireless Commun., vol. 7, no. 5, pp. 1669-1675, Jul. 2006.
  • J. Park, W. Jeong, H. Mahmoodi-Meimand, Y. Wang, H. Choo, and K. Roy, "Computation sharing programmable FIR ?lter for low-power and high-performance applications," IEEE J. Solid State Circuits, vol. 39, no. 2, pp. 348-357, Feb. 2004.
  • K.-H. Chen and T.-D. Chiueh, "A low-power digit-based recon?gurable FIR ?lter," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 617-621, Aug. 2006.
  • R. Mahesh and A. P. Vinod, "New recon?gurable architectures for implementing FIR ?lters with low complexity," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 2, pp. 275-288, Feb. 2010.
  • S. Y. Park and P. K. Meher, "Ef?cient FPGA and ASIC realizations of a DA-based recon?gurable FIR digital ?lter," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 7, pp. 511-515, Jul. 2014.
  • P. K. Meher, "Hardware-ef?cient systolization of DA-based calculation of ?nite digital convolution," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 707-711, Aug. 2006.
  • " target="_blank">RIS
    |
  • E. Mirchandani, R. L. Zinser, Jr., and J. B. Evans, "A new adaptive noise cancellation scheme in the presence of crosstalk speech signals]," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 10, pp. 681-694, Oct. 1995.
  • D. Xu and J. Chiu, "Design of a high-order FIR digital ?ltering and variable gain ranging seismic data acquisition system," in Proc. IEEE Southeastcon, Apr. 1993, p. 1-6.
  • J. Mitola, Software Radio Architecture: Object-Oriented Approaches to Wireless Systems Engineering. New York, NY, USA: Wiley, 2000.
  • A. P. Vinod and E. M. Lai, "Low power and high-speed implementation of FIR ?lters for software de?ned radio receivers," IEEE Trans. Wireless Commun., vol. 7, no. 5, pp. 1669-1675, Jul. 2006.
  • J. Park, W. Jeong, H. Mahmoodi-Meimand, Y. Wang, H. Choo, and K. Roy, "Computation sharing programmable FIR ?lter for low-power and high-performance applications," IEEE J. Solid State Circuits, vol. 39, no. 2, pp. 348-357, Feb. 2004.
  • K.-H. Chen and T.-D. Chiueh, "A low-power digit-based recon?gurable FIR ?lter," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 617-621, Aug. 2006.
  • R. Mahesh and A. P. Vinod, "New recon?gurable architectures for implementing FIR ?lters with low complexity," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 2, pp. 275-288, Feb. 2010.
  • S. Y. Park and P. K. Meher, "Ef?cient FPGA and ASIC realizations of a DA-based recon?gurable FIR digital ?lter," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 7, pp. 511-515, Jul. 2014.
  • P. K. Meher, "Hardware-ef?cient systolization of DA-based calculation of ?nite digital convolution," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 707-711, Aug. 2006.
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