Design Implementation of Successive Approximation Register A/D Converter
Keywords:
Analog to Digital Converters (ADCs), Successive Approximation (SAR), Flash ADC, Propagation delay, Offset Voltage, Power Dissipation Spurious Free Dynamic Range (SFDR).Abstract
This paper presents design implementation of Successive Approximation Register ADC. The ADC is the main building block in modem signal processing and communication systems. Main purpose of the ADC is to convert analog input into an equivalent digital output. There are many ADCs depending on the application like Sigma Delta ADC, Pipelined ADC, SAR ADC. The Successive Approximation Register (SAR) ADC is the most widely used converter in industrial control applications. It has good ratio of speed/power and has compact size that make this converter into an inexpensive device. A low power 8-bit 200MS/s Successive Approximation Register Analog to Digital Converter is designed and implemented in 180nm TSMC CMOS VLSI process. To reduce the complexity of design TG based D Flip-flop and charge scaling DAC are used. To increase the conversion rate and reduce the overall power dissipation of ADC Dynamic Latch Comparator is used.
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