Design Enhance AES Data Encryption and Decryption

Abstract

Advance Encryption Standard (AES), it is used to specify a Federal Information Processing Standard (FIPS) approved cryptographic algorithm that can be used to protect our electronic data. This paper present the AES algorithm with regard to Field Program Gate Array (FPGS), offers a very fast method and most customizable solution. The approach in order to minimize the hardware consumption for the transformation of Encryption and Decryption are simulated using an iterative design. Implementation of code carried out in Xilinx ISE 9.2i. In this paper, we present the implementation of the AES 128-bit encryption and decryption. AES Encryption is a method for scrambling data. A key is used to mix up data such that it can be securely stored or transfer over a network. The design is based on substitution and permutation network. In this system we have message, a plain text and a secret key. The 128 bits cipher text block is produce after the round function is processed plaintext block.