Design and Analysis of SRAM and DRAM using Microwind Software

Authors

  • Abhilesh Kedar  Department of Electronics and Telecommunication Engineering S. B. Jain Institute of Technology, Management and Research, Nagpur, Maharashtra, India
  • Aditya Verma  Department of Electronics and Telecommunication Engineering S. B. Jain Institute of Technology, Management and Research, Nagpur, Maharashtra, India
  • Latika Raut  Department of Electronics and Telecommunication Engineering S. B. Jain Institute of Technology, Management and Research, Nagpur, Maharashtra, India
  • Pinki Kumbhare  Department of Electronics and Telecommunication Engineering S. B. Jain Institute of Technology, Management and Research, Nagpur, Maharashtra, India
  • Rajashree Karoo  Department of Electronics and Telecommunication Engineering S. B. Jain Institute of Technology, Management and Research, Nagpur, Maharashtra, India
  • Rajeshree Zade  Department of Electronics and Telecommunication Engineering S. B. Jain Institute of Technology, Management and Research, Nagpur, Maharashtra, India
  • Prof. Omprakash K. Piprewar  Department of Electronics and Telecommunication Engineering S. B. Jain Institute of Technology, Management and Research, Nagpur, Maharashtra, India

Keywords:

SRAM, DRAM, MICROWIND, CMOS Technology

Abstract

This study analyses an minimizing the power consumption during write and stand by operation and propagation delay during write in 6T SRAM cell and 1T1C DRAM cell. And these cells are designed using Microwind3.5 Software in 45 nm and 32 nm CMOS Technology. The 6T architecture of SRAM cell is implemented using 32 nm CMOS Technology and Result have been compare with that of 45 nm CMOS Technology. Also the 1T1C architecture of DRAM cell is implemented using 32 nm CMOS Technology and Result have been compare with that of 45 nm CMOS Technology. The result of the delay and power dissipation of SRAM and DRAM with the applied power supply is presented. The graph of Voltage vs Time is plotted using Microwind3.5 software.

References

  1. Peter Bukelani Musiiwa and Shyam Akashe ," Comparative Evaluation of different 3T DRAM Cells at 45nm Technology" International Conference on Communication Networks (lCCN), 2015
  2. Saraju P. Mohanty, "CSCI 5330 Digital CMOS VLSI Design", University of North Texas.
  3. P. Upadhyay, R. Mehra and N. Thakur "Low Power Design of an SRAM Cell for Portable Devices" Int'l Conf. on Computer & Communication Technology IICCCI' 101 pp. 255-259.
  4. Saurabh and P. Shrivastav, "Low Power 6T-SRAM", IEEE 2012, 978-1-4673-3136.
  5. Sadulla Shaik† and Prathiba Jonnala, "Performance Evaluation of Different SRAM Topologies using 180,90,45 nm Technology", International Conference on Renewable Energy and sustainable energy, 2013, 978-1-4799-2075
  6. Acida V.V., Mohamed Salih K.K., "Design Of Low Power High Density SRAM Bit Cell", International Research Journal of Engineering and Technology, Vol.4, Issue 4, June 2017 e-ISSN: 2395 -0056, p-ISSN: 2395-0072
  7. Prateek Asthana, Sangeeta Mangesh, "PERFORMANCE COMPARISON OF 4T, 3T AND 3T1D DRAM CELL DESIGN ON 32 NM TECHNOLOGY", 2014 pp. 121–133, 2014.
  8. Chakka Sri Harsha Kaushik, Rajiv Reddy Vanjarlapati, Vaada Murali Krishna, Tadavarthi Gautam and V Elamaran, "VLSI Design of Low Power SRAM Architectures for FPGAs",

International Journal of Scientific Research in Science and Technology

Downloads

Published

2018-01-30

Issue

Volume 4, Issue 3, January-February-2018

Section

Research Articles

License

Copyright (c) IJSRST

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Abhilesh Kedar, Aditya Verma, Latika Raut, Pinki Kumbhare, Rajashree Karoo, Rajeshree Zade, Prof. Omprakash K. Piprewar, " Design and Analysis of SRAM and DRAM using Microwind Software, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 4, Issue 3, pp.390-395, January-February-2018.