Design of CMOS 8-Bit Parallel Adder Energy Efficient Structure using SR-CPL Logic Style

Authors

  • Aravinth. T. S  Assistant Professor,Department of Electronics & Communication Engineering, Karpagam Academy of Higher Education (Deemed to be University), Coimbatore, Tamil Nadu, India
  • Sundar. R  Assistant Professor,Department of Electronics & Communication Engineering, Karpagam Academy of Higher Education (Deemed to be University), Coimbatore, Tamil Nadu, India
  • Felix Muthu  PG Scholar Department of Electrical & Electronics Engineering Karpagam College of Engineering, Coimbatore, Tamil Nadu, India

Keywords:

SR-CPL logic Styles, PDP, DPL, Pass Transistor, Logic, Virtuoso Cadence Environment.

Abstract

We present high speed and low power 8-Bit parallel adder cells designed with modified SR-CPL logic styles that had a reduced power delay product (PDP) as compared to the previous logics DPL and pass transistor logic. We have carried out a comparison against other parallel adders reported as having a low PDP, in terms of speed and power consumption. All the parallel adders were designed with a 0.18µm CMOS technology virtuoso cadence environment. Simulations of the circuit show that the proposed parallel adders have reduced the power from 0.33mW to 0.24mW.

References

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International Journal of Scientific Research in Science and Technology

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Published

2017-04-30

Issue

Volume 3, Issue 5, May-June-2017

Section

Research Articles

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How to Cite

[1]
Aravinth. T. S, Sundar. R, Felix Muthu "Design of CMOS 8-Bit Parallel Adder Energy Efficient Structure using SR-CPL Logic Style " International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011,Volume 3, Issue 5, pp.30-34, May-June-2017.