Design And Implementation of Synchronous Binary Counter with Variable Clock for Real Time Applications
Keywords:
Backward Carry Propagation, Binary Counter, Constant-Time Counter, Pre-Scaled Counter.Abstract
In this work, a new fast structure for synchronous binary counting, which has a minimal counting period for practical counters. In many applications, a synchronous binary counter is necessary to be quick and handle a wide bit-width. However, most of the previous counters are associated with a limited counting rate due to large fan-outs and long carry chains, especially when the counter size is not small. In this paper, we first adopt a 1-bit Johnson counter to reduce the overall hardware complexity, and then duplicate the 1-bit Johnson counter to decrease the propagation delay caused by large fan-outs. Implementation results show that the proposed design can be realized with a small number of flip-flops, which is almost linear to the counter size thereby neglecting minimum delays and considering only the maximum delay path of the sub counters implemented in the proposed design. The effectiveness of the proposed method is synthesized and simulated using Xilinx ISE14.7.
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