High Performance, Area Efficient Ternary Content Addressable Memory (TCAM) With Fast Mapping and Updating Algorithm
Keywords:
Content-addressable memory (CAM), fast mapping algorithm, fast updating algorithm, random access memory (RAM)-based CAM.Abstract
Because of their high-speed lookup, content-addressable memory (CAMs) are utilized in a wide range of applications, including IP filtering, data compression, as well as artificial neural networks. Fast mapping as well as update methods for a binary CAM (FMU-TCAM) were provided in this article, which effectively use lookup tables, slice registers, as well as block random access memory (RAMs) on the Xilinx FPGA to imitate faster mapping as well as updated CAMs. The suggested approach has the advantage of directly using the CAM key as a location, which aids in the updating of memory unit contents. In remapping the CAM words including the updating word, CAMs in the literature consume the whole CAM depth, resulting in increased update latency
References
- A. Madhavan, T. Sherwood, and D. B. Strukov, “High-throughput pattern matching with CMOL FPGA circuits: Case for logic-in-memory computing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 12, pp. 2759–2772, Dec. 2018.
- R. Govindaraj and S. Ghosh, “Design and analysis of sttram-based ternary content addressable memory cell,” ACM J. Emerg. Technol. Comput. Syst., vol. 13, no. 4, p. 52, 2017.
- Z. Ullah, M. K. Jaiswal, Y. C. Chan, and R. C. C. Cheung, “FPGA implementation of SRAM-based ternary content addressable memory,” in Proc. IEEE 26th Int. Parallel Distrib. Process. Symp. Workshops PhD Forum, May 2012, pp. 383–389.
- Z. Ullah, M. K. Jaiswal, and R. C. C. Cheung, “E-TCAM: An efficient SRAM-based architecture for TCAM,” Circuits, Syst., Signal Process., vol. 33, no. 10, pp. 3123–3144, Oct. 2014.
- Z. Ullah, M. K. Jaiswal, and R. C. C. Cheung, “Z-TCAM: An SRAM based architecture for TCAM,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 2, pp. 402–406, Feb. 2015.
- M. Irfan, Z. Ullah, and R. C. C. Cheung, “Zi-CAM: A power and resource efficient binary content-addressable memory on FPGAs,” Electronics, vol. 8, no. 5, p. 584, May 2019.
- Z. Ullah, K. Ilgon, and S. Baeg, “Hybrid partitioned SRAM-based ternary content addressable memory,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, pp. 2969–2979, Dec. 2012.
- Z. Ullah, M. K. Jaiswal, R. C. C. Cheung, and H. K. H. So, “UETCAM: An ultra-efficient SRAM-based TCAM,” in Proc. IEEE Region Conf. (TENCON), Nov. 2015, pp. 1–6.
- S.-H. Yang, Y.-J. Huang, and J.-F. Li, “A low-power ternary content addressable memory with pai-sigma matchlines,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 10, pp. 1909–1913, Oct. 2012.
- B.-D. Yang, Y.-K. Lee, S.-W. Sung, J.-J. Min, J.-M. Oh, and H.-J. Kang, “A low power content addressable memory using low swing search lines,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 12, pp. 2849–2858, Dec. 2011
Downloads
Published
Issue
Section
License
Copyright (c) IJSRST

This work is licensed under a Creative Commons Attribution 4.0 International License.