Hierarchical Dynamic Key Generation and Selective Transformation Model for Optimized AES Block Cipher Core
Keywords:
AES (Advanced Encryption Standard), FPGA (field programmable gate array), LUT (Look up table), Mbps (megabit per second), sub (sub bytes), shift (shift rows), mix (mix column), add (add round key).Abstract
The inadequacies inherent in the existing cryptosystem have driven the development of new optimal hardware architecture and to exploit the benefits of cipher key characteristics and associated key generation tasks in cryptosystems for high-performance security systems. In this work, some of the prominent issues related to the existing AES core system, namely, lack of data rate, vulnerability towards attacks, reliability and discriminative key management problems are considered and solved using appropriate hierarchical transformation measures. Here inner stage pipelining is introduced over composite field based S-box transformation models to reduce the path delay. In addition to that, this work also includes some bit level masking technique for AES which constitutes simpler arithmetic such as inverter and modulo operation. With improved diffusion and confusion metrics this bit masking transformation model mitigates key management related issues in AES. An extensive analysis of data rate performance proved that proposed AES model offers improved system performance as compared to conventional AES core and robustness of improved FF masking model and associated security improvements in AES system is also proved with appropriate test input stimulus models.
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