Design and Synthesis of Multi-Operand Parallel Prefix Adder for Pseudorandom Bit Generator Applications

Authors

  • Korrapati Vyasa Purnima  Student, Dept of ECE, Shree Institute of Technical Education, Tirupati, Andhra Pradesh, India.
  • K. Mohana Krishna  Asst.Professor, Dept of ECE, Shree Institute of Technical Education, Tirupati, Andhra Pradesh, India.

Keywords:

Binary Adder, Parallel prefix adders, Pseudorandom bit generators, Cryptography.

Abstract

Numerous cryptographies as well as pseudorandom bit generator (PRBG) algorithms are employing the 3-operand binary adder as the basic functional block to accomplish modular arithmetic. It is also used in a variety of other purposes. To realize the three-operand binary addition, the current technique includes a high-speed as well as area-efficient adder design related to pre-bit - wise addition with carry prefix processing mechanism. In relation to previous suggested approach such as the 3 operands carry save adder and the 2 operands oriented three operand HCA. Rather than the Han-Carlson adder, we were employing the Ladner Fischer adder. Because this takes up less space and has a shorter latency. The synthesis and simulation are verified by employing Xilinx ISE 14.7 Tool.

References

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International Journal of Scientific Research in Science and Technology

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Published

2022-10-30

Issue

Volume 9, Issue 5, September-October-2022

Section

Research Articles

License

Copyright (c) IJSRST

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Korrapati Vyasa Purnima, K. Mohana Krishna "Design and Synthesis of Multi-Operand Parallel Prefix Adder for Pseudorandom Bit Generator Applications" International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011,Volume 9, Issue 5, pp.493-498, September-October-2022.