Vedic Multiplier Using Efficient Compressor to Reduce Delay for Vedic Multiplier : A Review

Authors

  • Ankita V. Rekkawar  M. Tech Scholar, Dept of Electronics and Comm., Ballarpur Institute of Technology, Ballarpur, Maharashtra, India
  • Prof. Atul Khode  Assistant Professor, Dept of Electronics and Comm., Ballarpur Institute of Technology, Ballarpur, Maharashtra, India
  • Prof. S Kuntawar  Assistant Professor, Dept of Electronics and Comm., Ballarpur Institute of Technology, Ballarpur, Maharashtra, India

Keywords:

R High Speed Multiplier, 4:2 Compressors, 7:2 Compressor, Modified Architecture, Vedic Mathematics, Array Multiplier, FPGA.

Abstract

With the coming of new innovation in the space of VLSI, correspondence and flag handling, there is a perpetually going interest for the rapid preparing and low territory design. The speed of a processor enormously relies on upon its time rather than a full snake and equipped for playing out this current multiplier's execution. This thusly builds the interest for fast multipliers, in the meantime remembering low territory and direct power utilization . In the course of recent decades, a few new structures of multipliers have been composed and investigated. Multipliers in view of the Booth's and changed Booth's calculation is very well known in present day VLSI configuration however joined their own arrangement of drawbacks. In these calculations, the increase procedure, includes a few middle of the road operation before touching base at the last answer.

References

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International Journal of Scientific Research in Science and Technology

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Published

2017-06-30

Issue

Volume 3, Issue 4, May-June-2017

Section

Research Articles

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How to Cite

[1]
Ankita V. Rekkawar, Prof. Atul Khode, Prof. S Kuntawar "Vedic Multiplier Using Efficient Compressor to Reduce Delay for Vedic Multiplier : A Review" International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011,Volume 3, Issue 4, pp.250-253, May-June-2017.