VLSI Architecture for DSP Application
Keywords:
Compressors, Counters, Xilinx, FPGAAbstract
Most present day arithmetic processors are worked with models that have been settled in the writing, with a considerable lot of the most recent developments dedicated to extraordinary technologies circuits and the utilization of cutting-edge innovations. In particular, the plan of multipliers is basic in digital signal processing applications, where a high number of increases are required. We have limited the number of adders by presenting diverse compressors. The twofold counter property has been converged with the compressor property to grow high request compressors, for example, 5-3 and 7-3 compressors partitioning, simulated annealing, and analytical placement).
References
- Khushboo Bais*, Zoonubiya Ali , “Design Of a High-Speed Wallace Tree Multiplier”, International Journal of Engineering Sciences & Research Technology, June, 2016.
- C.-A. Shen, C.-P. Yu and C.-H. Huang, “Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO WirelessCommunications With Convolutional Codes,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 2, pp. 587–599, Feb. 2016.
- Jorge Tonfat, Ricardo Reis,” Low Power 3-2 and 4-2 Adder Compressors Implemented Using ASTRAN” Published in Circuits and Systems (LASCAS), 2012 IEEE Third Latin American Symposium on 29 Feb.-2 March 2012.
- Ravi Nirlakalla, Thota Subba Rao, Talari JayachandraPrasad,”Performance Evaluation of High Speed Compressors for High Speed Multipliers” SERBIAN JOURNAL OFELECTRICAL ENGINEERING, Vol. 8, No. 3, November 2011,293-306.
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