Implementation of High Speed Double Tail Comparator

Abstract

In recent years, with the advance of wireless communication systems, microelectronics and sensor technologies, wireless sensor networks (WSNs) are becoming a hot-spot for scientific research and industrial applications. High speed and low power comparators are very much essential in the design of a very good analog to digital converter. In this paper a novel high speed, low offset voltage and low power double tail comparator is designed and simulated. The proposed design does not use any preamplifier stages before the latch stage, which accounts for the direct reduction of power dissipation and silicon area. For power optimization, the MOSFETs of the input differential pair comparator are designed to operate in sub-threshold region rather than in saturation region. The designed double tail comparator consumes 366µW when operated from a 1.8V power supply. The operating speed of the design is 100MHz and exhibits a propagation delay of 600µs. The simulated propagation delay is found to be 600µs and the entire design of the proposed double tail comparator circuit is carried out in 180nm CMOS technology and verified using the cadence-spectre simulator.