Configurable Fir Filter Using Different Multiplier Technique

Authors

  • Anubhav Shankhwar  Research scholar, Department of Electronics and Comm., RGPV Bhopal (M.P.), SRCEM Banmore, Morena, India
  • Shweta Agarwal  Assistantce professor, Department of Electronics and Comm., RGPV Bhopal (M.P.), SRCEM Banmore, Morena, India

Keywords:

FIR filter, Multiplier, Digital filter, DSPs, FPGA, MCSA, CSA, VLSI.

Abstract

Finite-Impulse Response (FIR) filler is playing the role of the backbone of the modern communication systems. The filler is mainly used to separate the required signals from the unwanted signals. During the separation the number of algorithms are employed which are responsible for the filtration speed. Today’s era of technology demands the maximum operating frequency. In order the boost the filtration the components of filler must be efficient. The speed of FIR filter is mainly depends on multiplier used in it. For this reason the FIR filler which is depicted here have the highly efficient multiplier. This presented filler can also configure for the different filtering co-efficient. Transpose form finite-impulse response (FIR) filters are naturally pipelined and support various consistent multiplications (MCM) technique that results in significant saving of computation. However, transpose form structure does not directly support the block processing unlike direct-form configuration. In this paper, we explore the possibility of realization of block FIR filter in transpose form configuration for area-delay efficient realization of large order FIR filters for both fixed and reconfigurable applications. Based on a detailed computational analysis of transpose form configuration of FIR filter, we have derived a flow graph for transpose form block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose form FIR filter. We have derived a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A low-complication design is using by the MCM scheme is also presented for the block implementation of fixed FIR filters. The proposed structure involves significantly less area-delay product (ADP) and less energy per sample (EPS) than the existing block implementation of direct-form structure for medium or large filter lengths, while for the short-length filters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure.

References

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Published

2018-07-30

Issue

Section

Research Articles

How to Cite

[1]
Anubhav Shankhwar, Shweta Agarwal, " Configurable Fir Filter Using Different Multiplier Technique, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 4, Issue 9, pp.93-98, July-August-2018.