A High-Performance FIR filter Architecture for Reconfigurable Applications

Abstract

Transpose form ?nite-impulse response (FIR) ?lters are characteristically pipelined and support multiple constant multiplications (MCM) procedure that results in signi?cant saving of calculation. However, transpose form con?guration does not specifically support the block performing not like direct-form con?guration. In this paper, we investigate the possibility of realization of block FIR ?lter in transpose shape con?guration for area-delay ef?cient realization of huge order FIR ?lters for both ?xed applications. Based on a detailed computational investigation of transpose form con?guration of FIR ?lter, we have derived a ?ow diagram for transpose shape block FIR ?lter with reduced register complexity. A detailed block formulation is detailed for transpose form FIR ?lter. We have inferred a general multiplier-based architecture for the proposed transpose form block ?lter for recon?gurable applications. A reduced-complex design using multiple constant multiplications scheme is also showed for block implementation of ?xed FIR ?lters. The proposed architecture obtains less area, less delay and less power consumption compared with the existing architecture of direct form structure for medium or long filter lengths. For this project analysis for determining area, power and delay it uses Xilinx.