Hardware Efficient LED for IoT Applications Using B-RAM

Authors

  • aB. Charu Manjari  Velammal College of Engineering and Technology Viraganoor, Madurai-625009, Tamil Nadu, India
  • M S Nivetha Nandini  Velammal College of Engineering and Technology Viraganoor, Madurai-625009, Tamil Nadu, India
  • K Susmitha  Velammal College of Engineering and Technology Viraganoor, Madurai-625009, Tamil Nadu, India
  • Dr. A. Babu Karuppiah  Velammal College of Engineering and Technology Viraganoor, Madurai-625009, Tamil Nadu, India
  • Mr. R. Rajaraja  Velammal College of Engineering and Technology Viraganoor, Madurai-625009, Tamil Nadu, India

Keywords:

lightweight encryption algorithm, increase the speed, Block RAMs (BRAMs), reducing area utilization, Spartan 3 FPGA.

Abstract

This paper analyses to implement a hardware efficient light weight encryption algorithm based on Light Encryption Device (LED). The hardware efficiency of a LED is mainly determined by the implementation of the Substitute Cell and the Mix Columns operation. In order to increase the speed, these two round operations are combined into a single step called Transformation Box (T-Box). To implement the designed LED algorithm, we use an iterative architecture so that the hardware elements can be reused for every round operation. Further Block RAMs (BRAMs) are utilized for reducing area utilization. We use 64 bit plain text and 128 bit key size to get 64 bit cipher text which is targeted to Spartan 3 FPGA.

References

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Published

2021-04-10

Issue

Section

Research Articles

How to Cite

[1]
aB. Charu Manjari, M S Nivetha Nandini, K Susmitha, Dr. A. Babu Karuppiah, Mr. R. Rajaraja, " Hardware Efficient LED for IoT Applications Using B-RAM , International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 9, Issue 1, pp.923-926, March-April-2021.