Hardware Efficient LED for IoT Applications Using B-RAM
Keywords:
lightweight encryption algorithm, increase the speed, Block RAMs (BRAMs), reducing area utilization, Spartan 3 FPGA.Abstract
This paper analyses to implement a hardware efficient light weight encryption algorithm based on Light Encryption Device (LED). The hardware efficiency of a LED is mainly determined by the implementation of the Substitute Cell and the Mix Columns operation. In order to increase the speed, these two round operations are combined into a single step called Transformation Box (T-Box). To implement the designed LED algorithm, we use an iterative architecture so that the hardware elements can be reused for every round operation. Further Block RAMs (BRAMs) are utilized for reducing area utilization. We use 64 bit plain text and 128 bit key size to get 64 bit cipher text which is targeted to Spartan 3 FPGA.
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