VLSI Implementation of High-Performance Ternary Operand PPA for Fir Filter Application
Keywords:
Carry save adder, Three operand adder, Pseudo Random number Generator, cryptography.Abstract
The binary digits adder, which performs mathematical operations, is the fundamental operational element of several cryptographies as well as pseudo-random bit generator approaches. The ripple carry adder, the final CSA step, requires an additional delay to operate. The parallel prefix adders use more space even though performance in terms of latency is improved. Parallel prefix adders can also be used to build three operand adders. A novel, low delay, area-efficient adder has been developed to improve efficiency in terms of delay as well as area strategy is utilized. FIR Filter having the element of adders and multipliers as a design parameter. So, the main objective of the DSP field is to reduce the area and delay in filter designs. This design is less complex in terms of area hardware and delay than similar designs that have been used in the past. Using the Xilinx ISE 14.7 version tool, the findings of the performance study and simulations are validated.
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