Implementation of Modified PMOS Biased Sense Amplifier Using 180nm

Authors

  • Ayesha Farheen  PG Scholar, Department of ECE (VLSI & Embedded System), Sharnbasva University, Kalaburagi, India.
  • Renuka. B. J  Assistant Professor, Department of ECE, Sharnbasva University, Kalaburagi, India.

Keywords:

Sense delay, Sense Amplifier, lector approach, Power gating techniques.

Abstract

A sensing amplifier is a component of a semiconductor memory chip's circuitry. The functionality, performance, and reliability of core memory architectures are all influenced by sense amplifiers. Two circuits are defined in this study. The suggested PMOS biased sensing amplifier is implemented in this circuit, which produces the same output results as prior work, but with a much higher decreased sense delay and power dissipation due to lower output impedance attributed to the use of lector approach in power gating strategies. As a conclusion, the simulation results accomplish the same functions as traditional circuits while consuming less energy. Using Tanner EDA and 180nm technology file, the total performance of the proposed sense amplifiers was simulated and analyzed.

References

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International Journal of Scientific Research in Science and Technology

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Published

2022-08-30

Issue

Volume 9, Issue 4, July-August-2022

Section

Research Articles

License

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Ayesha Farheen, Renuka. B. J "Implementation of Modified PMOS Biased Sense Amplifier Using 180nm" International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011,Volume 9, Issue 4, pp.152-160, July-August-2022.