Design And Synthesis of Multi-Operand Parallel Prefix Adder for Pseudorandom Bit Generator Applications
Keywords:
CSA (Carry save adder), sklansky adder.Abstract
Cryptographic applications and pseudo random generator perform modular arithmetic three operand is the basic fundamental unit used in all these applications. For performing three operand additions, CSA (carry save adder) is one of the most widely used adders. But in CSA in the final stage, carry is propagated which impacts the delay. Prefix parallel adders are therefore employed to get around this. The parallel prefix adders use more space even though performance in terms of latency is improved. Parallel prefix adders can also be used to build three operand adders. A brand-new, high-speed, and hardware-efficient adder technique is used to boost performance in terms of latency and area. This adder approach uses four stages to achieve three operand addition. Since Han Carlson adder is used in third stage, the suggested adder is not area efficient. To overcome this, in this paper we are replacing the Han Carlson parallel prefix adder with sklansky adder.
References
- M. M. Islam, M. S. Hossain, M. K. Hasan, M. Shahjalal, and Y. M. Jang, FPGA implementation of high-speed area-efficient processor for elliptic curve point multiplication over prime field, IEEE Access, vol. 7, pp. 178811–178826, 2019.
- Z. Liu, J. GroBschadl, Z. Hu, K. Jarvinen, H. Wang, and I. Verbauwhede, Elliptic curve cryptography with efficiently computable endomorphisms and its hardware implementations for the Internet of Things, IEEE Trans. Comput., vol. 66, no. 5, pp. 773–785, May 2017.
- Z. Liu, D. Liu, and X. Zou, An efficient and flexible hardware implementation of the dual-field elliptic curve cryptographic processor, IEEE Trans. Ind. Electron., vol. 64, no. 3, pp. 2353–2362, Mar. 2017.
- B. Parhami, Computer Arithmetic: Algorithms and Hardware Design. New York, NY, USA: Oxford Univ. Press, 2000
- P. L. Montgomery, Modular multiplication without trial division, Math. Comput., vol. 44, no. 170, pp. 519–521, Apr. 1985.
- S.-R. Kuang, K.-Y. Wu, and R.-Y. Lu, Low-cost high-performance VLSI architecture for montgomery modular multiplication, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 2, pp. 434–443, Feb. 2016.
- S.-R. Kuang, J.-P. Wang, K.-C. Chang, and H.-W. Hsu, Energy-efficient high-throughput montgomery modular multipliers for RSA cryptosystems, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 11, pp. 1999–2009, Nov. 2013.
- S. S. Erdem, T. Yanik, and A. Celebi, A general digit-serial architecture for montgomery modular multiplication, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 5, pp. 1658–1668, May 2017.
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