Hierarchical Dynamic Key Generation and Selective Transformation Model for Optimized AES Block Cipher Core
Keywords:
AES (Advanced Encryption Standard), FPGA (field programmable gate array)Abstract
Symmetric key cryptography, Hash functions and public key cryptography. Symmetric key algorithms namely Advanced Encryption Standard (AES), and Data Encryption Standard use the same key for encryption and decryption. This research examined a brand-new rapid picture key extraction from image. To create a key stream with outstanding statistical properties from picture have to use image processing. An effective and safe image based key AES S- is presented in this research. First, an image has to be selected after that by using image. The proposed architecture includes 8-bit data path and five main blocks. We design two specified register banks, Key-Register and State-Register, for storing the plain text, keys, and intermediate data. In order to increase security, the proposed Bio-Metric 256-bit AES method is heavily used for key management. A FPGA implementation therefore reduces power as a result of this. The suggested implementation's proposed throughput (Mbps) using Virtex-7 (xc7vx485tffg1157) FPGA improved.
References
- M. Rajeswara Rao, Dr.R.K.Sharma, SVE Department, NIT Kurushetra FPGA Implementation of combined S box and Inv S box of AES 2017 4th International conference on signal processing and integrated networks (SPIN).
- Nalini C. Iyer ; Deepa ; P.V. Anandmohan ; D.V. Poornaiah Mix/InvMixColumn decomposition and resource sharing in AES.
- Xinmiao Zhang, Student Member, IEEE, and Keshab K. Parhi, Fellow, High Speed VLSI architectures for the AES Algorithm, IEEE. VOL.12. No.9. September 2004
- Shrivathsa Bhargav, larry Chen, abhinandan Majumdar, Shiva Ramudit 128 bit AES Decryption, CSEE 4840 – Embedded system Design spring 2008, Columbia University.
- Atul M. Borkar ; R. V. Kshirsagar ; M. V. Vyawahare FPGA implementation of AES algorithm.
- Announcing the ADVANCED ENCRYPTION STANDARD (AES), November 26 2001.
- Yulin Zhang ; Xinggang Wang; Pipelined implementation of AES encryption based on FPGA 2010 IEEE International Conference on Information Theory and Information Security.
- Yuwen Zhu ; Hongqi Zhang ; Yibao Bao ; Study of the AES Realization Method on the Reconfigurable Hardware 2013 International Conference on Computer Sciences and Applications.
- Tsung-Fu Lin ; Chih-Pin Su ; Chih-Tsun Huang ; Cheng-Wen Wu; A high-throughput low-cost AES cipher chip Proceedings. IEEE AsiaPacific Conference on ASIC.
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