Approximate Multiplier Design Using Novel 4 : 2 Compressor Design With Improved Accuracy

Authors

  • Gurasala. JeevanaJyothi  PG Scholar, Department of ECE, Shree Institute of Technical Education, Tirupati, Andhra Pradesh, India
  • T. Sesha Giri  Professor, Department of ECE, Shree Institute of Technical Education, Tirupati, Andhra Pradesh, India

Keywords:

Approximate 4:2 compressors, approximate multipliers, error resilient applications, image processing.

Abstract

Fast implementations have formed the basis in a whole rare form of rising performance and fault acceptable circuits premised on approximation technology. High performance comes at the expense of accuracy in many applications. Additionally, such methods minimise system architectural complexity, latency, and power consumption. When compared to existing designs, this study investigates and proposes the design and analysis of an approximation compressor with reduced size, latency, and power and equivalent accuracy. The stated approximation 4: 2 compressor now has relatively small footprint, lower power losses, and reduced latency in comparison with precise 4: 2 compressor. With the optimized compressors, 8 bit and 16 bit Dadda multipliers can be designed efficiently. In comparison to current approximation multipliers, these multipliers offer equivalent accuracy.

References

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Published

2022-10-30

Issue

Section

Research Articles

How to Cite

[1]
Gurasala. JeevanaJyothi, T. Sesha Giri "Approximate Multiplier Design Using Novel 4 : 2 Compressor Design With Improved Accuracy" International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011,Volume 9, Issue 5, pp.423-429, September-October-2022.