Area and Power Efficient Multipliers Using Approximate Compressors and Full Adders for DSP Applications
Keywords:
Approximate full adder, inaccurate multiplier, and approximate compressor.Abstract
In this project, a new approximate full adder is proposed and applied in the reduction stages of multiplier. Using the current approximate 4-2 compressors as well as proposed approximate full adder designs are used for developing an 8-bit multiplier. For applications that are error robust, approximate computing can lessen design complexity while boosting performance and power efficiency. We can learn a lot from marginally inaccurate outputs in the majority of multimedia apps. Consequently, we are not required to create precise outcomes. In order to benefit from the relaxation of numerical exactness, this brief discusses a new technique to gate level logic modification for full adder approximation. The sum term of the conventional full adder is altered to reduce an area complexity. The effectiveness of the proposed method is synthesized and simulated using Xilinx Vivado.
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