High Performance ALU design using Energy Efficient Borrow Select Subtractor

Abstract

The fundamental architecture of any processor, or ALU, is a key factor in determining how efficiently it operates. Addition and subtraction is considered to be an important operation in ALU so the circuit which performs these operations has a drastic impact on the processor’s performance. The pace of operation in the subtraction process is determined by the sequential borrow bit, which travels from LSB to MSB encompassing all bits in the operands. Two modified borrow choose subtractor designs with improved area efficiency and lower power consumption are used in the proposed ALU circuit. As a result,a lesser number of gates are used for the logical flow of the subtraction process by employing blocks with fewer logic gates, which results in a reduction in the number of devices, area, and power dissipation. The proposed designs were implemented using Xilinx ISE 14.7 tool.