VLSI Design and Implementation of Multipliers Based on Approximate 2-Bit LUT Adders for Fault Tolerant Applications
Keywords:
Approximate computing, approximate adder, FPGA, low error, low power, LUT.Abstract
A methodology for constructing low-error, high-efficiency approximate adders has been provided in this project. To reduce the inaccuracy of approximation adders, the suggested solution effectively utilizes FPGA resources. We propose two approximate adders for FPGAs using our methodology: low error as well as area efficient approximate adder (LEADx), as well as area as well as power efficient approximate adder (APEx). Both approximate adders are composed of an accurate as well as an approximate part. The approximate parts of these adders are designed in a systematic way to minimize the mean square error (MSE). LEADx has lower MSE than the approximate adders in the literature. APEx has smaller area as well as lower power consumption than the other approximate adders than the existing adders. As a case study, In video encoding applications, approximation adders are employed. In the video encoding application, LEADx outperformed the other approximation adders. As a result, our proposed approximate adders can be used to create error-tolerant applications in FPGAs with efficiency. The effectiveness of the proposed method is synthesized as well as simulated using Xilinx ISE 14.7.
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