Implementation of Novel Approximate Adder Using Parallel Prefix Structure
Keywords:
Error Distance, Approximate Adder.Abstract
This article offers a unique approximation adder which uses error-reduced carry prediction and constant reduction in conjunction with error reduction techniques. The suggested adder design actually improve computing accuracy while also improving hardware effectiveness. In comparison to the approximate adders studied in this research, the proposed carry forecast technique can elevate prediction error rates. The error reduction technique also enhances overall computation efficiency by lowering the error distance (ED). The suggested adder is one of the most economical because it has the effective design compromise of the adders beneath analysis. We also show that whenever the postulated adder is used in application areas such as digital image processing and machine learning, the approximation errors caused by the adder have even less influence on quality attributes.
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