[1]
“VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture Using Clock Gating”, Int J Sci Res Sci & Technol, vol. 12, no. 1, pp. 658–666, Feb. 2025, Accessed: Aug. 01, 2025. [Online]. Available: https://ijsrst.com/index.php/home/article/view/IJSRST25121205