[1]
“Enhancing Power Efficiency in FIR Filter VLSI Architecture for Seismic Signal Processing with Clock Gating”, Int J Sci Res Sci & Technol, vol. 12, no. 2, pp. 866–874, Apr. 2025, Accessed: Aug. 13, 2025. [Online]. Available: https://ijsrst.com/index.php/home/article/view/IJSRST251222634