Enhancing Power Efficiency in FIR Filter VLSI Architecture for Seismic Signal Processing with Clock Gating. Int J Sci Res Sci & Technol [Internet]. 2025 Apr. 12 [cited 2025 Aug. 13];12(2):866-74. Available from: https://ijsrst.com/index.php/home/article/view/IJSRST251222634