Implementation of Segmentation Based Efficient Imprecise Multipliers with Mux Based Full Adders

Abstract

We offer a new method for multiplying two unsigned binary values using a Segmentation-based Approximate Multiplier in this paper. The primary problem for approximate multiplier systems is to decrease the area and latency while avoiding substantial errors. Almost every approximation multiplier on the market divides the input operands in order to take advantage of flow parallelism. The suggested design shrinks a Partial Products Matrix of the order of nx(2n-1) to a Reduced Partial Product Matrixof the order of 4x2n. It also removes the need for additional hardware for partial product compression and rearrangement. Along with this effort, we also present -SAM, an optimized version of our fundamental concept. SAM reduces the basic design's on-chip space and power use even more. Xilinx Vivado is used to simulate and synthesize the efficiency of the suggested technique.