Implementation of TSPC Flip-flop using Power Gating Technique

Authors

  • Triveni Jagadi  PG Scholar, Department of ECE (VLSI & EMBEDDED SYSTEM), Sharnbasva University, Kalaburagi, India
  • Vilaskumar Patil  Associate Professor, Department of ECE, Sharnbasva University, Kalaburagi, India

Keywords:

Power gating, D Flip-flop, Low voltage applications, TSPC.

Abstract

Power optimization is a very crucial issue in low voltage applications. This paper presents a design of D-Flip-Flop circuit using header power gating technique for low power operation. The primary goal of the design is to examine the power dissipation of D Flip-Flop in the proposed design style. The proposed design is implemented in Tanner EDA. The simulation results show that there is a significant reduction in power consumption for the proposed cell with power gating.

References

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International Journal of Scientific Research in Science and Technology

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Published

2022-08-30

Issue

Volume 9, Issue 4, July-August-2022

Section

Research Articles

License

Copyright (c) IJSRST

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Triveni Jagadi, Vilaskumar Patil "Implementation of TSPC Flip-flop using Power Gating Technique" International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011,Volume 9, Issue 4, pp.361-366, July-August-2022.